SLVUC07A December   2020  – May 2021 TPS543320

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  3. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Switching Frequency (FSEL Pin)
    3. 2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
    4. 2.4 Adjustable UVLO
  4. 3Test Setup and Results
    1. 3.1  Input/Output Connections
    2. 3.2  Efficiency
    3. 3.3  Output Voltage Regulation
    4. 3.4  Load Transient and Loop Response
    5. 3.5  Output Voltage Ripple
    6. 3.6  Input Voltage Ripple
    7. 3.7  Synchronizing to a Clock
    8. 3.8  Start-up and Shutdown with EN
    9. 3.9  Start-up and Shutdown with VIN
    10. 3.10 Hiccup Current Limit
    11. 3.11 Overvoltage Protection
    12. 3.12 Thermal Performance
  5. 4Board Layout
    1. 4.1 Layout
  6. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  7. 6Revision History

3.2 Efficiency

Figure 3-1 through Figure 3-4 show the efficiency for both designs on the TPS543320EVM. Using the selection jumpers for U2, the results for different output voltage and switching frequency combinations are included. The test points listed in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the contribution of PCB parasitic power loss to the measured power loss.

The following are some additional test setup considerations to minimize external sources of power dissipation.

  • Disable the other regulator to avoid including the switching quiescent current of the other regulator in the efficiency measurement.
  • Do not measure the SW pin of U2 with TP28 while measuring the efficiency of U2. Measuring the SW pin with this test point loads this node with 500 Ω and the efficiency measurement will include the power lost in this external resistance.
  • Remove the shunts from J11 and J13 as a small amount of power is dissipated in the EN resistor divider connected to U2.

Table 3-3 Efficiency Measurement Test Points
RELATED IC TEST POINT NAME REFERENCE DESIGNATOR FUNCTION
U1 VIN_U1 TP1 Input voltage test point connected near pins of U1
VOUT_U1 TP2 Output voltage test point near output inductor of U1
PGND_EFF_U1 TP5 PGND reference test point for both input and output voltages Kelvin connected near U1
U2 VIN_U2 TP12 Input voltage test point connected near pins of U2
VOUT_U2 TP15 Output voltage test point near output inductor of U2
PGND_EFF_U2 TP17 PGND reference test point for both input and output voltages Kelvin connected near U2
GUID-20201208-CA0I-KMVV-B0JP-CZQGMH6NGGVN-low.gif
VOUT = 1.8 V fSW = 1500 kHz
Figure 3-1 U1 Efficiency
GUID-20201208-CA0I-XPBN-WLMB-D0MXFGMZVSMF-low.gif
VIN = 12 V fSW = 1000 kHz
Figure 3-3 U2 Efficiency – 1000-kHz Switching Frequency with Different Output Voltages
GUID-20201208-CA0I-P2ZT-KCJH-03KG7NWQMG51-low.gif
VOUT = 3.3 V fSW = 1000 kHz
Figure 3-2 U2 Efficiency – Default Configuration
GUID-20201209-CA0I-NX3N-ML43-HQK5QLM4GWJJ-low.svgGUID-20201208-CA0I-XPBN-WLMB-D0MXFGMZVSMF-low.gif
VIN = 9 V VOUT = 3.3 V
Figure 3-4 U2 Efficiency – 3.3-V Output with Different Switching Frequencies