SLVUC07A December   2020  – May 2021 TPS543320

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  3. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Switching Frequency (FSEL Pin)
    3. 2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
    4. 2.4 Adjustable UVLO
  4. 3Test Setup and Results
    1. 3.1  Input/Output Connections
    2. 3.2  Efficiency
    3. 3.3  Output Voltage Regulation
    4. 3.4  Load Transient and Loop Response
    5. 3.5  Output Voltage Ripple
    6. 3.6  Input Voltage Ripple
    7. 3.7  Synchronizing to a Clock
    8. 3.8  Start-up and Shutdown with EN
    9. 3.9  Start-up and Shutdown with VIN
    10. 3.10 Hiccup Current Limit
    11. 3.11 Overvoltage Protection
    12. 3.12 Thermal Performance
  5. 4Board Layout
    1. 4.1 Layout
  6. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  7. 6Revision History

Synchronizing to a Clock

Figure 3-23 shows U1 and U2 synchronized to an external clock of 1.25 MHz at the SYNC test point. To synchronize to the clock at the SYNC test point, place a shunt on the ENSYNC_U1 or ENSYNC_U2 jumper or jumpers to enable the output of the buffers.

Figure 3-24 shows the transitions to and from synchronizing to an external clock with 3-A load. 16 pulses with a frequency of 1-MHz were sent to the SYNC testpoint on the EVM. In this waveform, after ten pulses, the TPS543320 begins synchronizing to the clock. After the clock goes away, the TPS543320 switches at 70% of the internal clock frequency for four pulses then transitions back to the normal internal clock frequency. There is only a small variation in the output voltage during these transitions.

GUID-20201130-CA0I-JF9T-Q87K-23H3G43WKXBZ-low.pngFigure 3-23 U1 and U2 Synchronized to a Clock
GUID-20201130-CA0I-SXC0-G8BN-BDLV5CJ0QGGV-low.pngFigure 3-24 U2 Clock Synchronization Transitions