SLVUC22 July   2021 TPS62912 , TPS62913

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Performance Specification
    2. 1.2 EVM Features and Modifications
      1. 1.2.1 Input and Output Capacitors
      2. 1.2.2 Enable Level Shifter and Adjustable Threshold Voltage
      3.      Power Good Level Shifter
      4. 1.2.3 NR/SS Capacitor
      5. 1.2.4 Feedforward Capacitor
      6. 1.2.5 S-CONF Resistor
      7. 1.2.6 Loop Response Measurement
      8. 1.2.7 Single LC Filter Operation
  3. 2Setup
    1. 2.1 Input/Output Connector Descriptions
    2. 2.2 Ripple Measurement
  4. 3Test Results
  5. 4Board Layout
  6. 5Schematic and Bill of Materials
    1. 5.1 Schematic
  7. 6Bill of Materials

Power Good Level Shifter

The TPS6291x has a power good (PG) function to indicate when the output voltage has reached the proper level. The PG pin is an open-drain output that requires a pull-up resistor. Because the VOUT is the IC ground in an IBB configuration, the PG pin is referenced to VOUT instead of ground, which means that the device pulls PG to VOUT when it is low. This can cause difficulties in systems that are not able to withstand negative voltages on the PG detection circuit. A level shifter circuit similar to the EN/SYNC implementation is used.

When using the PG function, a voltage (VCC) must be applied on J6. This voltage must not be driven higher than 18V + VOUT. So for a -5 V output, VCC must be less than 12 V.

A 10K resistor pull-up is connected to the PG pin of the device through Q2A. When the PG pin output is low, Q2A is low, causing Q2B to see VCC, which causes the SYS_PG signal to be pulled to GND. This can be seen on pin 1 of J7.

When the PG pin output is high, Q2A is high, causing Q2B to see VOUT, which causes the SYS_PG signal to be pulled to VCC.