In this PDN, the PMIC devices have the
following four configured power states:
- Standby
- Active
- MCU Only
- Suspend-to-RAM
In Figure 6-1, the configured PDN power states are shown, along with the transition conditions
to move between the states. Additionally, the transitions to hardware states, such
as SAFE RECOVERY and LP_STANDBY are shown. The hardware states are part of the Fixed
Device Power Finite State Machine (FSM) and described in the TPS6594-Q1 data sheet,
see Section 8.
When the PMICs transition from the FSM
to the PFSM, several initialization instructions are performed to disable the
residual voltage checks on both the BUCK and LDO regulators and set the
FIRST_STARTUP_DONE bit. After these instructions are executed the PMICs wait for a
valid ON Request (SU_ACTIVE trigger) before entering the ACTIVE state. The
definition for each power state is described below:
STANDBY
The PMICs are powered by a valid supply on the system power rail (VCCA >
VCCA_UV). All device resources are powered down in the STANDBY state. EN_DRV
is forced low in this state. The processor is in the Off state, no voltage
domains are energized. Refer to the Section 6.3.2 sequence description.
ACTIVE
The PMICs are powered by a valid supply. The PMICs are fully functional and
supply power to all PDN loads. The processor has completed a recommended
power up sequence with all voltage domains energized in both MCU and Main
processor sections. Refer to the Section 6.3.8 sequence description.
MCU ONLY
The PMICs are powered by a valid supply. Only the power resources assigned
to the processor MCU rails are on. Refer to the Section 6.3.7 sequence description.
A special case of the MCU ONLY mode is when the state is entered due to an
SOC power error. In this case the, the PMICs cannot transition to the
ACTIVE or other states until the PMICs are intentionally moved to the MCU
ONLY state by the processor. After this triggering of the TO_MCU sequence
and 'reentery' into the MCU ONLY state can the PMICs transition back to the
ACTIVE state.
Suspend-to-RAM (S2R)
The PMICs are powered by a valid supply. Only 3 SoC voltage domains
(vdds_ddr_bias, vdds_ddr, and vdds_ddr_c) remain energized while all other
domains are off to minimize total system power. EN_DRV is forced low in this
state. Refer to the Section 6.3.9 sequence description.