SLVUC72C October   2021  – November 2022 TPSI3050-Q1

 

  1.   Abstract
  2.   Trademarks
  3.   General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  4. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
  5. 2Connection Descriptions
  6. 3Operating Modes
    1. 3.1 Two-Wire Mode
    2. 3.2 Three-Wire Mode
  7. 4Load Configurations
  8. 5Schematic
  9. 6Layout
  10. 7Bill of Materials
  11. 8Revision History

3.2 Three-Wire Mode

Figure 3-6 Three-Wire Mode Simplified Schematic

Use three-wire mode for applications that require higher levels of power transfer and the fastest enable and disable switch times the TPSI3050-Q1 can offer. In this mode, power transfers from the primary to secondary side independent of the enable pin state. Setting EN pin high or low asserts the VDRV to drive the external power MOSFETs or SCRs.

To configure the EVM for three-wire mode, the following changes must be made:

  1. J2 header allows to supply VDDP directly or indirectly through an LDO with a 5-V output.
    1. Supply VDDP directly: place J2 shunt between positions 1-2. This action allows the user to supply VDDP directly.
      Figure 3-7 Three-Wire Mode VDDP Direct Supply
    2. Supply VDDP through LDO: place the J2 shunt between positions 2-3. The user can supply VDDP indirectly through an LDO with a 5-V output.
      Figure 3-8 Three-Wire Mode VDDP Supply Through 5-V LDO
  2. Supply the EN voltage using the terminal block J2.
    Table 3-2 Power Selection for Three-Wire Mode
    J4-Header

    Power Converter Duty Cycle (Three-Wire Mode, Nominal)

    PXFR #1 (7.32 kΩ)13.3%
    PXFR #2 (20 kΩ)93.3%

Measurements

Figure 3-10 shows the powering up delay from VDDP rising to VDDM and VDDP rising using the highest power transfer PXFR #2 (20 kΩ) in three-wire mode. The power up delay is directly related to the power transfer selection and to the capacitors from VDDH to VDDM and VDDM to VSSS. The delay from VDDP to VDDM is 330.5 us and the delay from VDDP to VDDH is 357.6 us. Figure 3-3 shows the delay from EN rising to VDRV rising using the highest power transfer PXFR #2 (20 kΩ) in three-wire mode. The delay from EN to VDRV is 3.145 us. Figure 3-11 shows the delay from EN falling to VDRV falling. The delay is 2.461 us.

Figure 3-9 Three-Wire Mode Powering Up
Figure 3-11 Three-Wire Mode Switching OFF
Figure 3-10 Three-Wire Mode Switching ON