SLVUC93 September   2021 TPSM63606

 

  1.   Trademarks
  2. 1High-Density EVM Description
    1. 1.1 Typical Applications
    2. 1.2 Features and Electrical Performance
  3. 2EVM Performance Specifications
  4. 3EVM Photo
  5. 4Test Setup and Procedure
    1. 4.1 EVM Connections
    2. 4.2 EVM Setup
    3. 4.3 Test Equipment
    4. 4.4 Recommended Test Setup
      1. 4.4.1 Input Connections
      2. 4.4.2 Output Connections
    5. 4.5 Test Procedure
      1. 4.5.1 Line/Load Regulation and Efficiency
  6. 5Test Data and Performance Curves
    1. 5.1 Efficiency and Load Regulation Performance
    2. 5.2 Waveforms
    3. 5.3 Bode Plot
    4. 5.4 Thermal Performance
    5. 5.5 EMI Performance
  7. 6EVM Documentation
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
    3. 6.3 PCB Layout
    4. 6.4 Assembly Drawings
    5. 6.5 Multi-Layer Stackup
  8. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Custom Design With WEBENCH® Tools
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation

4.2 EVM Setup

  • Use the VIN S+ and VIN S– test points along with the VOUT S+ and VOUT S– test points located near the power terminal blocks as voltage monitoring points where voltmeters are connected to measure the input and output voltages, respectively. Do not use these sense terminals as the input supply or output load connection points. The PCB traces connected to these sense terminals are not designed to support high currents.
  • Header J5 provides access to the following test points:
    • VIN
    • EN
    • SYNC
    • PGOOD
    • VOUT
    • BODE
    The SYNC test point provides a convenient location to connect an external clock signal. The power-good (PGOOD) test point is available to monitor when a valid output voltage is present on the EVM. Refer to Section 4.1 for specific information related to the various test points.
  • The VOUT SELECT header (J3) allows selection of the required output voltage:
    • 1.8 V
    • 2.5 V
    • 3.3 V
    • 5 V
    • 12 V
    Before applying power to the EVM, make sure that the jumper is present and properly positioned for the intended output voltage. Always remove input power before changing the jumper settings.
  • The FSW SELECT header (J4) allows selection of a suitable switching frequency:
    • 500 kHz
    • 750 kHz
    • 1 MHz
    • 1.5 MHz
    • 2 MHz
    This establishes an acceptable ripple current for the integrated buck inductor based on the circuit requirements, specifically the input voltage range and output voltage. Before applying power to the EVM, make sure that the jumper is present and properly positioned for the intended switching frequency. Always remove input power before changing the jumper settings.
Note:

Choose a switching freqeuency that aligns with the output voltage setting. For example, the following list contains typical settings that yield 30% to 40% inductor peak-to-peak ripple current and optimal slope compensation contribution:

  • 2.5 V at 500 kHz
  • 3.3 V at 750 kHz
  • 5 V at 1 MHz
  • 8 V at 1.5 MHz
  • 12 V at 2 MHz
Refer to the TPSM63606 data sheet, TPSM63606 Quickstart Calculator and WEBENCH® Power Designer for additional guidance pertaining to module setup and component selection.