SLVUCB3 March   2022

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Related Documentation
  3. 2Schematics, Bill of Materials, and Layout
    1. 2.1 TPS3760EVM Schematic
    2. 2.2 TPS3760EVM Bill of Materials
    3. 2.3 Layout and Component Placement
  4. 3EVM Connectors
    1. 3.1 EVM Test Points
    2. 3.2 EVM Jumpers
  5. 4EVM Setup and Operation
    1. 4.1 Input Power (VDD)
    2. 4.2 SENSE1/SENSE2 Inputs
    3. 4.3 RESET1/RESET2 Outputs
    4. 4.4 Capacitor Time Delay Reset/MR
    5. 4.5 Capacitor Time Delay Sense/MR

4.5 Capacitor Time Delay Sense/MR

The TPS3760 and TPS3760-Q1 family of devices contain two adjustable sense time delay pins that control the time with which the reset pins assert after they reach their invalid condition. The user can adjust the configuration of these pins via the jumpers located at J9 and J10. Header J9 serves as the selectable option for CTS1 and header J10 serves as the selectable option for CTS2. The values of capacitors are labeled on the board and also in the jumper description section. For J9, they are, from bottom to top, DNI (for user defined capacitance), 1nF, 10nF, 100nF, 1uF, and 10uF. For J10, they are, from top to bottom, DNI (for user defined capacitance), 1nF, 10nF, 100nF, 1uF, and 10uF. Please see the Time Delay Configuration section on the TPS3760-Q1 datasheet for more detailed information on user programming.