SLVUCC7A January   2022  – September 2022 TPS629211-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Performance Specification
  5. 3EVM Configuration and Modification
    1. 3.1 Input and Output Capacitors
    2. 3.2 Configurable Enable Threshold Voltage
    3. 3.3 MODE/S-CONF Setting
    4. 3.4 Power Good
    5. 3.5 Power Good Pullup Voltage
    6. 3.6 Feedforward Capacitor Option
    7. 3.7 Output Voltage Setting
    8. 3.8 Loop Response Measurement
  6. 4EVM Test Setup
    1. 4.1 Input and Output Connectors
    2. 4.2 Jumper Configuration
      1. 4.2.1 JP1 Enable
      2. 4.2.2 JP2 MODE/S-CONF
      3. 4.2.3 JP3 Power Good
      4. 4.2.4 JP4 PG Pullup Voltage
  7. 5Test Results
  8. 6Board Layout
  9. 7Schematic and Bill of Materials
    1. 7.1 Schematic
    2. 7.2 Bill of Materials
  10. 8References
  11. 9Revision History

4.2.2 JP2 MODE/S-CONF

Table 4-3 MODE/S-CONF Pin Configuration
Jumper Short LocationDescription
Pin 1 and Pin 3Forced PWM, 2.5 MHz, external FB, output discharge enabled
Pin 3 and Pin 5Auto PFM/PWM with AEE, 2.5 MHz, external FB, output discharge enabled
Pin 2 and Pin 452.3 k to GND, Forced PWM, 2.5MHz, internal FB(VSET), output discharge disabled
Pin 4 and Pin 642.2 k to GND, Auto PFM/PWM, 2.5MHz, internal FB(VSET), output discharge disabled