SLVUCD0 February   2022 TPS7H5002-SP , TPS7H5003-SP , TPS7H5004-SP

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2EVM Setup and Quick Start Guide
  4. 3EVM Connectors and Test Points
  5. 4PCB Layouts
  6. 5Schematics
  7. 6Bill of Materials

3 EVM Connectors and Test Points

Table 3-1 is a list of major connections on the board. For further information, see the relevant section in the TPS7H5001-SP Radiation-Hardness-Assured Si and GaN Dual Output Controller data sheet. A ✓ means that the test point is included in the EVM.

Table 3-1 EVM Board Connections
Test Point

5001

5002

5003

5004

ConnectionDescription
TP1, J1

✓

✓

✓

✓

OUTAConnected to the gate driver in the design. Components R5, C5 can be used to test different R/C loads.
TP2, J2✓✓OUTBConnected to the gate driver in the design. Components R6, C6 can be used to test different R/C loads.
TP3, J3✓✓✓SRAConnected to the gate driver in the design. Components R7, C7 can be used to test different R/C loads.
TP4, J4✓SRBConnected to the gate driver in the design. Components R8, C8 can be used to test different R/C loads.
TP5, TP6✓✓✓✓CS_LIMInput for current sense in the design. The CS_LIM circuit provides small triangle waveform from OUTA, OUTB. Note that this can load OUTA, OUTB causing a slow in the slew rate. If R9 and R10 are unpopulated, CS_LIM can be force from TP5.
TP7✓✓✓✓VINVoltage input for the TPS7H5001/2/3/4EVM-CVAL device
TP8✓✓✓✓ENEnable pin for the TPS7H5001/2/3/4EVM-CVAL device, currently pulled high to VLDO
TP9✓✓✓✓COMPError amplifier output for the TPS7H5001/2/3/4EVM-CVAL, forcing this voltage runs the TPS7H5001/2/3/4EVM-CVAL in open loop.
TP10✓✓✓✓REFCAPInternal reference for TPS7H5001/2/3/4EVM-CVAL
TP11, TP12✓✓✓✓SSIn a closed loop design, this slowly increases converter output voltage during start-up
TP13, TP15✓✓✓✓SYNCInputting a clock on this pin synchronizes the TPS7H5001/2/3/4EVM-CVAL to a frequency half of the input frequency
TP14✓✓✓✓VLDOInternal voltage rail for device logic
TP20✓✓✓✓VSENSEVoltage sense for the TPS7H5001/2/3/4EVM-CVAL. Connected to converter output voltage in the full design.
TP21✓✓✓✓RSCSlope compensation selection resistor. Sets slope compensation slew rate internal to the device.
TP22✓✓✓✓HICCConfigurability for the hiccup time of the converter. While grounded through a resistor on the EVM, in a full design it is generally a capacitor.
TP23✓✓✓✓FAULTA signal high on this node turns the TPS7H5001/2/3/4EVM-CVAL off for any fault condition needed
TP24✓✓SPConfigurability for the delay between the synchronous rectifiers and main output
TP25✓✓✓✓RTFrequency select for the TPS7H5001/2/3/4EVM-CVAL. Change this to vary the frequency of the converter.
TP26✓✓PSConfigurability for the delay between the main output and synchronous rectifiers
TP27✓✓✓LEBConfigurability for the leading edge blanking time of the converter

Table 3-2 describes and lists the connections and configuration for J6. Use J6 to switch between different DCL connections to test different duty cycle limits. Pin 1 is noted by the dot next to the pin.

Table 3-2 J6 Connections and Configuration
Pin ConnectionDuty Cycle Limit Configuration Description
Pin 1 and Pin 2100%DCL is connected high to VLDO,

Used for TPS7H5001/2/3 EVM variants

Pin 2 and Pin 350%DCL is connected low to AVSS,

Used for TPS7H5001/4 EVM variants

Floating75%DCL is left floating,

Used for TPS7H5001/2/3 EVM variants