5 PCB Layout

Figure 5-1 through Figure 5-6 show the PCB layout images, including 3D views and copper layers. The PCB is 62 mils standard thickness with 2-oz copper on all four layers as shown in Table 5-1. The PCB is also optimized for EMI performance. The layout minimizes the area of high dv/dt nodes like SW and BOOT with the addition of a snubber circuit to attenuate SW node ringing. The small high-frequency ceramic input capacitors are placed very close to the IC to minimize the loop formed from VIN pins, through the capacitor, to the PGND pins. The board also features an EMI filter on the back-side of the board with options for an inductor, ferrite bead, and filter capacitors to tune the filter's EMI performance.

Figure 5-1 3D Top View

Figure 5-2 3D Bottom View

Figure 5-3 Top Layer Copper

Figure 5-4 Layer 2 Copper

Figure 5-5 Layer 3 Copper

Figure 5-6 Bottom Layer Copper (Top View)