Use three-wire mode for applications that require higher levels of power transfer and the fastest enable and disable switch times the TPSI3052-Q1 can offer. In this mode, power transfers from the primary to secondary side independent of the enable pin state. Setting EN pin high or low asserts the VDRV to drive the external power MOSFETs or SCRs.
To configure the EVM for three-wire mode, the following changes must be made:
J2 header allows to supply VDDP directly or indirectly through an LDO with a 5-V output.
Supply VDDP directly: place J2 shunt between positions 1-2. This action allows the user to supply VDDP directly.
Figure 3-7 Three-Wire Mode VDDP Direct Supply
Supply VDDP through LDO: place the J2 shunt between positions 2-3. The user can supply VDDP indirectly through an LDO with a 5-V output.
Figure 3-8 Three-Wire Mode VDDP Supply Through 5-V LDO
Supply the EN voltage using the terminal block
J2.
Table 3-2 Power Selection for
Three-Wire Mode
J4-Header
Power
Converter Duty Cycle (Three-Wire Mode, Nominal)
PXFR #1 (7.32 kΩ)
13.3%
PXFR #2 (20 kΩ)
93.3%
Measurements
Figure 3-9 shows the powering up delay from VDDP rising to VDDM and VDDP rising using the highest power transfer PXFR #2 (20 kΩ) in three-wire mode. The power up delay is directly related to the power transfer selection and to the capacitors from VDDH to VDDM and VDDM to VSSS. The delay from VDDP to VDDM is 425.7 us and the delay from VDDP to VDDH is 395 us. Figure 3-9 shows the delay from EN rising to VDRV rising using the highest power transfer PXFR #2 (20 kΩ) in three-wire mode. The delay from EN to VDRV is 3.141 us. Figure 3-11 shows the delay from EN falling to VDRV falling. The delay is 2.489 us.