SLVUCJ7 October 2023 TPS25730
The PD controller transmits the contents of this register as a Sink_Capabilities message after receiving a Get_Sink_Cap message unless its configuration or USB PD rules require a different response in the context.
Writes to this register have no immediate effect. The PD controller updates and uses this register each time it must send a Sink Capabilities message.
Address | Name | Access | Length | Unique Per Port | Power-Up Default |
---|---|---|---|---|---|
0x33 | TX_SINK_CAPS | RW | 29 | yes | Initialized by Application Configuration |
Bits | Name | Description | |
---|---|---|---|
Bytes 26-29: PDO #7 (treated as a 32-bit little endian value) | |||
31:0 | TXSinkPDO7 | Seventh Sink Capabilities PDO contents. See Table 2-6. | |
Bytes 22-25: PDO #6 (treated as a 32-bit little endian value) | |||
31:0 | TXSinkPDO6 | Sixth Sink Capabilities PDO contents. See Table 2-6. | |
Bytes 18-21: PDO #5 (treated as a 32-bit little endian value) | |||
31:0 | TXSinkPDO5 | Fifth Sink Capabilities PDO contents. See Table 2-6. | |
Bytes 14-17: PDO #4 (treated as a 32-bit little endian value) | |||
31:0 | TXSinkPDO4 | Fourth Sink Capabilities PDO contents. See Table 2-6. | |
Bytes 10-13: PDO #3 (treated as a 32-bit little endian value) | |||
31:0 | TXSinkPDO3 | Third Sink Capabilities PDO contents. See Table 2-6. | |
Bytes 6-9: PDO #2 (treated as a 32-bit little endian value) | |||
31:0 | TXSinkPDO2 | Second Sink Capabilities PDO contents. See Table 2-6. | |
Bytes 2-5: PDO #1 (treated as a 32-bit little endian value) | |||
31:0 | TXSinkPDO1 | First Sink Capabilities PDO contents. See Table 2-5. | |
Byte 1: Header | |||
7:3 | Reserved | ||
2:0 | numValidPDOs |
Each PDO in this TX_SINK_CAPS register follows the definition from the USB PD specification, reproduced below for convenience. For more details on the meaning of each field refer to the USB PD specification.
Bits(s) | Description |
---|---|
31:30 | Supply Type, this shall always be set to 00b (Fixed Supply) |
29 | Dual-Role Power, this is overridden by the logical OR of the ProcessSwapToSink, ProcessSwapToSource, InitiateSwapToSink, and InitiateSwapToSource fields in the PORT_CONTRL register. |
28 | Higher Capability |
27:26 | Reserved |
25 | Dual-Role Data, this is overridden by the logical OR of the ProcessSwapToUFP, ProcessSwapToDFP, InitiateSwapToUFP, and InitiateSwapToDFP fields in the PORT_CONTRL register. |
24:20 | Reserved |
19:10 | Voltage |
9:0 | Operational Current |
Bits(s) | Description | |||
---|---|---|---|---|
Fixed Supply | Variable Supply | Battery Supply | APDO (PPS) | |
31:30 | 00b | 01b | 10b | 11b |
29:28 | Reserved. | Maximum Voltage | Maximum Voltage | 00b |
27:25 | Reserved | |||
24:20 | MaxPpsVoltage | |||
19:17 | Voltage | Minimum Voltage | Minimum Voltage | |
16 | Reserved | |||
15:10 | MinPpsVoltage | |||
9:8 | Operational Current | Operational Current | Operational Power | |
7 | Reserved | |||
6:0 | MaxPpsCurrent |