SLVUCK7A
november 2022 – july 2023
TPSF12C1
,
TPSF12C1-Q1
1
Description
Get Started
Features
Applications
6
1
Evaluation Module Overview
1.1
Introduction
1.2
Kit Contents
1.3
Specifications
1.4
Device Information
2
Hardware
2.1
EVM Description
2.2
Setup
2.2.1
High-Voltage Testing
2.2.2
EVM Connections
2.2.3
Low-Voltage Testing
2.3
Header Information
2.4
EVM Performance Validation
2.5
AEF Design Flow
2.5.1
AEF Circuit Optimization and Debug
3
Implementation Results
3.1
EMI Performance
3.2
Thermal Performance
3.3
Surge Immunity
3.4
SENSE and INJ Voltages
3.5
Insertion Loss
4
Hardware Design Files
4.1
Schematic
4.2
Bill of Materials
4.3
PCB Layout
4.3.1
Assembly Drawings
4.3.2
Multi-Layer Stackup
5
Compliance Information
5.1
Compliance and Certifications
6
Additional Information
Trademarks
7
Related Documentation
7.1
Supplemental Content
8
Revision History
3.5
Insertion Loss
Figure 3-8
Typical Insertion Loss with AEF Enabled and Disabled