SLVUCK7A november   2022  – july 2023 TPSF12C1 , TPSF12C1-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Description
    2. 2.2 Setup
      1. 2.2.1 High-Voltage Testing
      2. 2.2.2 EVM Connections
      3. 2.2.3 Low-Voltage Testing
    3. 2.3 Header Information
    4. 2.4 EVM Performance Validation
    5. 2.5 AEF Design Flow
      1. 2.5.1 AEF Circuit Optimization and Debug
  9. 3Implementation Results
    1. 3.1 EMI Performance
    2. 3.2 Thermal Performance
    3. 3.3 Surge Immunity
    4. 3.4 SENSE and INJ Voltages
    5. 3.5 Insertion Loss
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout
      1. 4.3.1 Assembly Drawings
      2. 4.3.2 Multi-Layer Stackup
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1.     Trademarks
  13. 7Related Documentation
    1. 7.1 Supplemental Content
  14. 8Revision History

2.2.2 EVM Connections

The EVM daughter-card connects to the main EMI filter board through header J1. The sense and inject capacitors, along with a robust ground connection, interfaces the low-voltage EVM to the high-voltage power lines.

Header J1 provides an interface through terminals S1, S2, INJ and GND, as described in Table 3-1. Connect S1 and S2 to sense capacitors, designated as CSEN1 and CSEN2 in Figure 3-3. Connect the opposite terminals of the sense capacitors to the Live and Neutral power lines between the CM chokes, LCM1 and LCM2. Connect INJ to the inject capacitor, designated as CINJ, whose opposite terminal then connects to either the Live or Neutral power line as shown. The X-capacitor at this position, designated as CX2, sets a low impedance between the power lines from a CM standpoint – this means that a single inject capacitor is adequate for current injection. Finally, connect a nominal 12-V bias supply from VDD to GND to power the AEF circuit. The GND attachment point on the filter board corresponds to where the Y-capacitors in a passive design normally connect.

Refer to the diagram of Figure 3-3 for an example of component placement on a filter board, where the EVM header J1 can mount directly to receptacle J2.

GUID-20230717-SS0I-FZHT-QQHR-GLP4R2G4MBLT-low.svg Figure 2-3 Filter Component and EVM Placement Example