SLVUCL9A June   2023  – February 2025 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  TPS6521907 Sequence and Power Block Diagram
    3. 2.3  Enable Settings
    4. 2.4  Regulator Voltage Settings
    5. 2.5  Sequence Settings
      1. 2.5.1 Power-Up Sequence
      2. 2.5.2 Power-Down Sequence
    6. 2.6  EN / PB / VSENSE Settings
    7. 2.7  Multi-Function Pin Settings
    8. 2.8  Over-Current Deglitch
    9. 2.9  Mask Settings
    10. 2.10 Discharge Check
    11. 2.11 Multi PMIC Config
  6. 3Revision History

2.9 Mask Settings

This section describes the settings that are masked by default and the effect they have on the device state as well as the nINT pin.

Table 2-15 Mask Settings
Register AddressField NameValueDescription
Mask effects on device state and nINT pin0x25MASK_EFFECT0x3No state change, nINT reaction, bit set for Faults (same as 10b)
UV Mask0x24BUCK1_UV_MASK0x0un-masked (Faults reported)
0x24BUCK2_UV_MASK0x0un-masked (Faults reported)
0x24BUCK3_UV_MASK0x0un-masked (Faults reported)
0x24LDO1_UV_MASK0x0un-masked (Faults reported)
0x24LDO2_UV_MASK0x0un-masked (Faults reported)
0x24LDO3_UV_MASK0x0un-masked (Faults reported)
0x24LDO4_UV_MASK0x0un-masked (Faults reported)
Power-up retries/attempts0x24MASK_RETRY_COUNT0x0Device retries up to 2 times
Die Temperature0x25SENSOR_0_WARM_MASK0x0un-masked (Faults reported)
0x25SENSOR_1_WARM_MASK0x0un-masked (Faults reported)
0x25SENSOR_2_WARM_MASK0x0un-masked (Faults reported)
0x25SENSOR_3_WARM_MASK0x0un-masked (Faults reported)
Masking bit to control whether nINT pin is sensitive to PushButton (PB)0x25MASK_INT_FOR_PB0x1masked (nINT pin not sensitive to any PB events)
Masking bit to control whether nINT pin is sensitive to RV (Residual Voltage) 0x25MASK_INT_FOR_RV0x0un-masked (nINT pin pulled low for any RV events during transition to ACTIVE state or during enabling of rails)