SLVUCM0 august   2023 TPS65219

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521908 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config

3.10 Multi PMIC Config

The TPS65219 allows to synchronize multiple devices, in case more rails are required to be supplied. The GPIO (pin#16) is an input/output digital pin, however, the input-functionality is only used in multi-PMIC configuration. The I/O-configuration of the GPIO-pin is done by the MULTI_DEVICE_ENABLE bit in MFP_1_CONFIG register. The table below shows the default multi-device register setting. For more information about the TPS65219 multi-PMIC operation, please refer to the device data sheet available on ti.com.

Table 3-17 Multi-PMIC Configuration
Register Name Field Name Value Description
MFP_1_CONFIG MULTI_DEVICE_ENABLE 0x0 Single-device configuration, GPIO pin configured as GPO