Connect the EVM to the filter board using the
appropriate sense capacitors, inject capacitor and ground connection.
Apply a VDD bias supply voltage of 8 V to
16 V (nominal 12 V, with ripple voltage less than 20 mV peak-to-peak) between the VDD and
GND terminals of J1.
Measure the voltage at the INJ pin of the
TPSF12C3 (pin 13) with respect to GND; it should be a DC voltage of VVDD/2 and
have no AC perturbations that indicate instability. Check that the VDD current consumption
is approximately 12 mA at VVDD = 12 V. If the INJ pin voltage is oscillating,
modify the damping network components on the EVM to achieve stability.
The user must perform low-voltage testing
prior to connecting the high-voltage power stage. To provide a CM stimulus, connect a 5-V
peak-to-peak square-wave source from a function generator as shown in Figure 3-4. Set the signal frequency to the switching freqeuncy of the power stage
and choose a duty cycle that creates all the spectral harmonics (aside: 50% duty cycle
eliminates the even harmonics, 33.3% removes the triple-n harmonics, and so forth). A 1-nF
capacitor in series with the signal source emulates a practical CM noise source impedance.
Using the CM excitation source,
verify the dynamic voltage range of the TPSF12C3 INJ pin. Ensure that the INJ pin
voltage relative to GND operates in a window between 2.5 V and VVDD – 2
V.
Connect a LISN on each input power line
and measure the EMI with AEF disabled (EN tied to GND) to benchmark the existing passive
filter. Short the low-voltage (bottom) terminal of the inject capacitor to GND when AEF is
disabled by tying the INJ terminal on J1 to GND. This emulates the Y-capacitor connection
in an equivalent passive filter design.
Remove the pulldown short on the inject
capacitor and enable the AEF circuit by allowing EN to float high. Repeat the EMI
measurement, thus quantifying the EMI reduction with AEF.
In a similar fashion, perform a comparison of
filter insertion loss or attenuation performance using a network analyzer.
For a true insertion loss measurement with 50-Ω source and load impedances, replace the
LISN by a 50-Ω load tied from the power lines to GND.
Using high-voltage safety precautions,
connect the switching power stage as shown in Figure 3-3. Turn the regulator ON and, similar to step 4, verify that the IC's INJ
pin voltage is not getting clipped. To improve the dynamic range of the INJ voltage,
increase one or more of the following:
Regulator-side Y-capacitance, CY1,
CY2, CY3 and CY4
Inject capacitance,
CINJ
VDD supply voltage,
VVDD
Measure the EMI with AEF enabled and
disabled, similar to the procedure outlined in steps 5 and 6.
Turn the regulator OFF. Wait for all high-voltage capacitors to fully discharge.