SLVUCM5 july   2023 TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

4.7 Configuring the EN/PB/VSENSE Pin

The enable pin of the PMIC can be configured as Enable, Push-Button, or VSENSE. In addition to the function, the deglitch can also be configured. Additionally, this pin has the option for first supply detection (FSD) to ignore the state of the EN/PB/VSENSE pin during the first power-up.

  • Figure 4-8 shows the settings to be changed when using the TPS65219-GUI.

  • Table 4-19 show the register fields to be written when NOT using the TPS65219-GUI.

GUID-20230428-SS0I-KPST-XFGG-LWZTDTW2KKTD-low.svg Figure 4-8 EN/PB/VSENSE Configuration Using the TPS65219-GUI
Table 4-19 NVM Registers for EN / PB / VSENSE
Register Address Bit Settings
Bit # Field Name
First Supply Detection 0x20 7 PU_ON_FSD 0h = FSD Disabled

1h = FSD Enabled
Pin Configuration 5-4 EN_PB_VSENSE_CONFIG 0h = Enable

1h = Push Button

2h = VSENSE

3h = Enable
Deglitch 3 EN_PB_VSENSE_DEGL see register map on data sheet