SLVUCM5 july   2023 TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

4.4 Configuring GPIOs

GPIOs can be used to enable external discrete components. GPIO can also be used for multi-PMIC configuration to sync the power-up and power-down sequence between two TPS65219 devices.

  • Figure 4-5 shows the settings to be changed when using the TPS65219-GUI.

GUID-20230428-SS0I-6BCN-GX4D-NPMC3SLWXNJJ-low.svg Figure 4-5 GPIOs Configuration

Table 4-10 NVM Registers for GPIO Settings
Register Address Bit Settings
Bit # Field Name
Enable settings in Active state 0x1E 2 GPIO_EN 0h = Disabled. The output state is low.

1h = Enabled. The output state is Hi-Z.

1 GPO2_EN 0h = Disabled. The output state is low.

1h = Enabled. The output state is Hi-Z.

0 GPO1_EN 0h = Disabled. The output state is low.

1h = Enabled. The output state is Hi-Z.

Enable settings in Standby state 0x22 2 GPIO_STBY_E N 0h = Disabled. The output state is low.

1h = Enabled. The output state is Hi-Z.

1 GPO2_STBY_E N 0h = Disabled. The output state is low.

1h = Enabled. The output state is Hi-Z.

0 GPO1_STBY_E N 0h = Disabled. The output state is low.

1h = Enabled. The output state is Hi-Z.

Table 4-11 NVM Register for Multi-PMIC Configuration
Register Address Bit Settings
Bit # Field Name
GPO2 configuration 0x1F 3 MULTI_DEVICE_ENABLE 0h = Single-device configuration

1h = Multi-device configuration