SLVUCM5 july   2023 TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

4.9 Configuring Mask Settings

There are several interrupt settings that can be masked to bypass specific PMIC monitoring features or modify how PMIC reacts when interrupts are detected. The interrupts that can be masked include undervoltage monitoring, temperature monitoring, among others. Figure 4-10 shows the mask settings in the configuration tab of the GUI.

Note: If any of the Mask registers is not shown in the configuration tab of the TPS65219-GUI, they can be found in the Register Map which includes the full list of registers.

GUID-20230710-SS0I-SQQX-XXZ5-XPBG6QKJVSZD-low.svg Figure 4-10 Mask Settings in TPS65219-GUI
Table 4-21 MASK Settings on Register 0x1E
Register Address Bit
Bit# Field Name
0x1E 7 BYPASS_RAILS_DISCHA RGED_CHECK

Table 4-22 MASK Settings on Register 0x1E
Register Address Bit
Bit# Field Name
0x24 7 MASK_RETRY_COUNT
6 BUCK3_UV_MASK
5 BUCK2_UV_MASK
4 BUCK1_UV_MASK
3 LDO4_UV_MASK
2 LDO3_UV_MASK
1 LDO2_UV_MASK
0 LDO1_UV_MASK
Table 4-23 MASK Settings on Register 0x1E
Register Address Bit
Bit# Field Name
0x25 7 MASK_INT_FOR_PB
6-5 MASK_EFFECT
4 MASK_INT_FOR_RV
3 SENSOR_0_WARM_MASK
2 SENSOR_1_WARM_MASK
1 SENSOR_2_WARM_MASK
0 SENSOR_3_WARM_MASK