SLVUCM5 july   2023 TPS6521905 , TPS6521905-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Requirements for NVM Programming
  6. 3Typical NVM Flow
  7. 4Programming Instructions
    1. 4.1  Configuring Enable Settings
    2. 4.2  Configuring the Bucks
    3. 4.3  Configuring LDOs
    4. 4.4  Configuring GPIOs
    5. 4.5  Configuring Sequence
    6. 4.6  Configuring Multi-Function Pins
    7. 4.7  Configuring the EN/PB/VSENSE Pin
    8. 4.8  Changing I2C Address
    9. 4.9  Configuring Mask Settings
    10. 4.10 NVM Re-Programming
  8.   A Non-NVM Registers
  9.   B Loading a NVM Configuration File to PMIC
  10.   C PMIC Configurable Fields
  11.   D References

4.1 Configuring Enable Settings

The PMIC has an Active and Standby state where rails can be enabled or disabled. The state change can be triggered by the MODE/STBY pin when configured as STBY.

  • Figure 4-2 shows the settings to be changed when using the TPS65219-GUI.

  • Table 4-2 show the register fields to be written when NOT using the TPS65219-GUI.

GUID-20230504-SS0I-P4QD-6KDC-C4C2CZXX5LBP-low.svg Figure 4-2 Enable Settings Using the TPS65219-GUI
Table 4-1 NVM Registers for Enable Settings
Register Address Bit Settings
Bit # Field Name
Enable rails in Active state 0x02 6 LDO4_EN 0h = Disabled

1h = Enabled

5 LDO3_EN 0h = Disabled

1h = Enabled

4 LDO2_EN 0h = Disabled

1h = Enabled

3 LDO1_EN 0h = Disabled

1h = Enabled

2 BUCK3_EN 0h = Disabled

1h = Enabled

1 BUCK2_EN 0h = Disabled

1h = Enabled

0 BUCK1_EN 0h = Disabled

1h = Enabled

Enable rails in Standby state 0x21 6 LDO4_STBY_EN 0h = Disabled

1h = Enabled

5 LDO3_STBY_EN 0h = Disabled

1h = Enabled

4 LDO2_STBY_EN 0h = Disabled

1h = Enabled

3 LDO1_STBY_EN 0h = Disabled

1h = Enabled

2 BUCK3_STBY_EN 0h = Disabled

1h = Enabled

1 BUCK2_STBY_EN 0h = Disabled

1h = Enabled

0 BUCK1_STBY_EN 0h = Disabled

1h = Enabled