SLVUCM6 March   2024 TPS65219-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521923W-Q1 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config

3.10 Multi PMIC Config

The TPS65219 allows to synchronize multiple devices in case more rails are required. The input functionality of the GPIO is only used in a multi-PMIC configuration. The configuration of the GPIO-pin is done writing to the MULTI_DEVICE_ENABLE bit in the MFP_1_CONFIG register. The table below shows the default multi-device register setting. For more information about the TPS65219 multi-PMIC operation, please refer to the device data sheet available on ti.com.

Table 3-17 Multi-PMIC Configuration
Register Address Field Name Value Description
0x1F MULTI_DEVICE_ENABLE 0x0 Single-device configuration, GPIO pin configured as GPO