SLVUCN2A October   2023  – August 2024 DRV3901-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Overview
    1. 2.1 Connectors and Configuration Headers
    2. 2.2 Signal Test Points
    3. 2.3 LED Indicators
  6. 3EVM GUI Control Application
    1. 3.1 MSP430 FET Drivers
    2. 3.2 Cloud-based GUI
    3. 3.3 Local Installation
  7. 4EVM GUI Operation
    1. 4.1 Hardware Set-up
    2. 4.2 Launching the DRV3901-Q1EVM GUI Application
  8. 5GUI Overview
    1. 5.1 Programming the EVM
    2. 5.2 Saving and Loading Register Configurations
    3. 5.3 Scripting Window
  9. 6Pyro Fuse SPI Modes
    1. 6.1 Stand-alone SPI
    2. 6.2 Addressable SPI
  10. 7Revision History

2.2 Signal Test Points

Table 2-3 describes each MCU signal on header J4. There are two rows of header pins on each side. Normally need to keep shunts for all signals on J4 and P5/P6. Then MCU can communicate with DRV3901-Q1 driver with accessible SPI. Accessible SPI is default configuration for GUI.

Removing shunts on J4 disconnects the signal from the MCU. This allows the drivers to be controlled with an external controller.

Changing P5 and P6 configuration is used to change nSCS signal connection between. I case not to use accessible SPI but normal SPI, P5/P6 can set nSCS as normal SPI configuration

DRV3901-Q1 J4 MCU Signal Header Figure 2-2 J4 MCU Signal Header
Table 2-3 MCU signal header
SignalDescription

SDI

SDI signal

SDO

SDO signal

SCLK

SCLK signal

nSCS

nSCS signal for Driver A and B

TRIG1_A

HW pin trigger 1 for Driver A

TRG1_B

HW pin trigger 1 for Driver B

TRIG2_A

HW pin trigger 2 for Driver A

TRIG2_B

HW pin trigger 2 for Driver B

NAD_nFAULT_A

nFAULT signal for Driver A

NAD_nFAULT_B

nFAULT signal for Driver B