SLVUCN2A October   2023  – August 2024 DRV3901-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Overview
    1. 2.1 Connectors and Configuration Headers
    2. 2.2 Signal Test Points
    3. 2.3 LED Indicators
  6. 3EVM GUI Control Application
    1. 3.1 MSP430 FET Drivers
    2. 3.2 Cloud-based GUI
    3. 3.3 Local Installation
  7. 4EVM GUI Operation
    1. 4.1 Hardware Set-up
    2. 4.2 Launching the DRV3901-Q1EVM GUI Application
  8. 5GUI Overview
    1. 5.1 Programming the EVM
    2. 5.2 Saving and Loading Register Configurations
    3. 5.3 Scripting Window
  9. 6Pyro Fuse SPI Modes
    1. 6.1 Stand-alone SPI
    2. 6.2 Addressable SPI
  10. 7Revision History

6.2 Addressable SPI

Addressable SPI allows SPI communication with both drivers simultaneously. In this mode, one nSCS signal is connected to both drivers. Diagram in Figure 6-2 shows the SPI connections for addressable SPI. The register map will display the register values of the selected driver. To write to a specific driver, it has to be selected in the GUI.

DRV3901-Q1 Addressable SPI Diagram Figure 6-2 Addressable SPI Diagram

In order for communication to be successful with both drivers, the following has to be done:

  • The nFAULT/NAD resistor of each driver has to be different. The NAD resistors for each driver are selected in headers J3 and J8 (Table 2-2). The resistor value needs to match the resistor selected in the GUI .
Note: The NAD/nFAULT resistors are latched during DRV3901-Q1 power up. Ensure that the desired resistors for each driver are selected in the EVM before powering up the board.