SLVUCN5B July   2023  – July 2024 TPS7H6003-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Best Practices
      1.      General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  8. 3Implementation Results
    1. 3.1 Evaluation Setup
    2. 3.2 Performance Data and Results
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5References
  11. 6Revision History

Description

The TPS7H60x3EVM-CVAL and TPS7H60x5EVM uses an input voltage rail on J1/J2 to power the PVIN of a half-bridge FET stack. The user can either run the device without the rest of the power stage or add an inductor and capacitor on the provided pads. By default, the device runs PWM mode and IIM mode can be used with minimal changes. Inputting a 0-5V waveform on J9 or J6/J15 can be connected to the inputs of the TPS7H60x3-SP or TPS7H60x5-SEP to run the driver.