The TPS65219-Q1 PMIC is a cost and space optimized solution that has flexible mapping to support the power requirements from different processors and SoCs. This PMIC contains seven regulators; 3 Buck regulators and 4 Low Drop-out Regulators (LDOs). Additionally, it has I2C communication, GPIOs and configurable multi-function pins. TPS65219-Q1 is characterized for -40°C to +125°C ambient temperature. For safety sensitive applications, TPS65219-Q1 is functional safety capable. Therefore the TPS65219-Q1 development process is a TI-quality managed process, also functional safety FIT rate calculation and Failure mode distribution (FMD) is available. Whenever entering the INITIALIZE state, the PMIC reads its memory and loads the registers with the content from the EEPROM. The EEPROM loading takes approximately 2.3ms. The power-up sequence can only be executed after the EEPROM-load and all rails are discharged below the SCG threshold. This document describes the default configuration programmed on TPS6521920W-Q1.

The following sections describe the default configuration on the EEPROM-backed registers. During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked interrupt bits and DISCHARGE_EN bits.