SLVUCN8 april   2023 TPS65219-Q1

 

  1.   ABSTRACT
  2.   Trademarks
  3. 1Introduction
  4. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521920W-Q1 Sequence and Power Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config

2.4.3 TPS6521920W-Q1 Sequence and Power Block Diagram

GUID-20230216-SS0I-0TXG-3CWK-L6QNZTJDPHS3-low.svg Figure 2-1 TPS6521920W-Q1 Example Power Block Diagram
GUID-20230216-SS0I-NZL7-BPG9-RB9768BL6ZBK-low.svg Figure 2-2 TPS6521920W-Q1 Power-Up Sequence
Note:
  • tDEGL_EN_Rise_Fast is configurable on NVM. See register field “EN_PB_VSENSE_DEGL” on TRM for default value.
  • tREACTION_ON is not configurable. Refer to specifications table on TPS65219-Q1 data sheet.
GUID-20230216-SS0I-THMM-LSQW-9RPQS5RMXMB6-low.svg Figure 2-3 TPS6521920W-Q1 Power-Down Sequence
Note:
  • tDEGL_EN_Fall and tREACTION_OFF are not configurable. Refer to specifications table on TPS65219-Q1 data sheet.