SLVUCO6 june   2023 TPSI2072-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4.   General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  5. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
  6. 2Connection Descriptions
  7. 3Test Equipment
  8. 4Recommended Test Setup
    1. 4.1 Waveforms
    2. 4.2 VS1_ADC and VS2_ADC Voltage Dividers
  9. 5Schematic
  10. 6PCB Layout
  11. 7Interlayer Stitching Capacitor
    1. 7.1 Interlayer Stiching Capacitors & EMI Performance Improvements
    2. 7.2 VS1_ADC and VS2_ADC Voltage Dividers
  12. 8Bill of Materials
  13. 9Revision History

7 Interlayer Stitching Capacitor

GUID-20230613-SS0I-DSQ6-JFLL-QVKQTHX72XQB-low.png Figure 7-1 TPSI2072-Q1 EVM Test Setup

Ensure that the TPSI2072Q1EVM has the following setting on the jumpers:

  1. J7 – Shunt is connecting EN1 and EN1_EXT.
  2. J9 – Shunt is connecting EN2 and EN2_EXT.
  3. If not using a waveform generator as shown above, alternate setting the shunts to be between VDD and EN1/EN2. This action causes EN1/EN2 to be high when VDD is powered.