The EVM layout flows from left (VIN) to right (VOUT) with the input and output capacitors placed as close as possible to the TPS7H2201. Vias under the TPS7H2201 allow a thermal path from the top layer all the way to the bottom layer. The EVM does not populate all the input and output capacitors for the TPS7H2201 but has footprints that allow additional capacitors to be populated. While this provides flexibility to the customer for electrical evaluation, it does not reflect the best optimized area for the TPS7H2201 in a real application.

The following images show the TPS7H2201EVM board layers.

Figure 4-3 Top Overlay

Figure 4-4 Top Solder Mask

Figure 4-5 Layer 1 (Top)

Figure 4-6 Layer 2

Figure 4-7 Layer 3

Figure 4-8 Layer 4 (Bottom)

Figure 4-9 Bottom Solder