SLVUCS8 April   2024 TPS3842 , TPS3842-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Test Points
      2. 2.1.2 EVM Jumpers
    2. 2.2 EVM Setup and Operation
      1. 2.2.1 Capacitor Sense Time Delay
      2. 2.2.2 Capacitor Reset Time Delay
      3. 2.2.3 Input Power (VDD)
  7. 3Hardware Design Files
    1. 3.1 TPS3842EVM Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials
  8. 4Additional Information
    1. 4.1 Trademarks
  9. 5Related Documentation

PCB Layouts

Figure 4-2 and Figure 4-3 are the top overlay and bottom overlay of the printed circuit board (PCB) and shows the component placement on the EVM. Figure 4-4 shows the top layout, Figure 4-5 and Figure 4-6 show the top and bottom layers, and Figure 4-7 and Figure 4-8 show the top and bottom solder masks of the EVM.

GUID-20240415-SS0I-SMKC-MXNW-VWMS3CPNMZ2Q-low.svg Figure 3-2 Top Overlay
GUID-20240415-SS0I-CVBM-VJ0V-PNVSFLVMSV9Z-low.svg Figure 3-3 Bottom Overlay
GUID-20240415-SS0I-6QXP-XCBF-Z2QLD41GB2FJ-low.svg Figure 3-4 Top Layout
GUID-20240415-SS0I-FNVT-MDTQ-WZMV6HRWPBRK-low.svg Figure 3-5 Top Layer
GUID-20240415-SS0I-8HMT-WMJ1-VJ0PTB9HHHQN-low.svg Figure 3-6 Bottom Layer
GUID-20240415-SS0I-VJST-0N3G-L8WCM735CB7F-low.svg Figure 3-7 Top Solder Mask
GUID-20240415-SS0I-76H4-HPLL-MV6WBD8BB6PV-low.svg Figure 3-8 Bottom Solder Mask