SLVUCT9 January   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Trademarks
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Alternate Board Configurations
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Important Usage Notes
    3. 2.3 Connector Descriptions
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Sequence UP and DOWN Thresholds
    3. 3.3 Delay Timer
    4. 3.4 Regulation Timer
    5. 3.5 Disabled Channels
    6. 3.6 Externally Induced System RESET
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
  10. 6Additional Information
    1. 6.1 Known Hardware Issues
  11. 7Related Documentation
  12. 8Revision History

6.1 Known Hardware Issues

  1. An initial build of this board has duplicate designators for 2 test points. Both the RESET and EN1_S test points were listed as TP20. The schematic and BOM provided in this User Guide show the corrected version that will be visible on the silkscreen of future board builds, with EN1_S as TP20 and RESET as TP47.