SLVUCV3 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS652190C Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config
  7. 4Revision History

2.1 TPS652190C Sequence and Power Block Diagram

GUID-20231010-SS0I-D0MS-DWDB-JHWKMCLZ6CZF-low.svg Figure 2-1 TPS652190C Example Diagram
GUID-20231011-SS0I-VQMV-LHW9-L67QGXGBMSV9-low.svg Figure 2-2 TPS652190C Power-Up Sequence
GUID-20231011-SS0I-NTTG-GGGG-HB85WWWVMLRJ-low.svg Figure 2-3 TPS652190C Power-Down Sequence