SLVUCV3 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS652190C Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config
  7. 4Revision History

3.7 Over-Current Deglitch

This section describes the default settings for the over current deglitch. When any of these registers are set (value = 1b), it enabled the long-deglitch option for the corresponding rail.

Table 3-14 Over Current Deglitch
Register Address Field Name Value Description
0x23 EN_LONG_DEGL_FOR_OC_BUCK1 0x0 Deglitch duration for OverCurrent on BUCK1 is ~20us
0x23 EN_LONG_DEGL_FOR_OC_BUCK2 0x0 Deglitch duration for OverCurrent on BUCK2 is ~20us
0x23 EN_LONG_DEGL_FOR_OC_BUCK3 0x0 Deglitch duration for OverCurrent on BUCK3 is ~20us
0x23 EN_LONG_DEGL_FOR_OC_LDO1 0x0 Deglitch duration for OverCurrent on LDO1 is ~20us
0x23 EN_LONG_DEGL_FOR_OC_LDO2 0x0 Deglitch duration for OverCurrent on LDO2 is ~20us
0x23 EN_LONG_DEGL_FOR_OC_LDO3 0x0 Deglitch duration for OverCurrent on LDO3 is ~20us
0x23 EN_LONG_DEGL_FOR_OC_LDO4 0x0 Deglitch duration for OverCurrent on LDO4 is ~20us