SLVUCZ2 May   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Headers and Test Points Information
    2. 2.2 Connector Information
    3. 2.3 Indicator LEDs
    4. 2.4 Hardware Setup
  9. 3Software
    1. 3.1 Web GUI Access or Local GUI Installation
    2. 3.2 Connecting EVM to GUI
    3. 3.3 GUI Overview
    4. 3.4 DRV8000-Q1EVM
      1. 3.4.1 Register Map
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Trademarks

Headers and Test Points Information

DRV8000-Q1EVM, DRV8000-Q1EVM (MD084-001) (Top
                    View) Figure 2-1 DRV8000-Q1EVM (MD084-001) (Top View)
CAUTION: Hot surface temperature. The EVM can have high surface temperatures marked by the FIRE triangular symbol on the EVM. Avoid touching the marked hot surface area when driving high currents to prevent potential burn damage.
DRV8000-Q1EVM, DRV8000-Q1EVM Header and Test
                    Point Information Figure 2-2 DRV8000-Q1EVM Header and Test Point Information
Table 2-1 Header and Test Point Description - DRV8000-Q1EVM
Component label Description
Aee XDS110 header between MSP432E401Y and MSPM0G3507.
B

Main signal header:

  • GD_IN1: Half-bridge and H-bridge control input 1.
  • GD_IN2: Half-bridge and H-bridge control input 2.
  • PWM1: PWM input 1 for regulation of all drivers except electrochrome.
  • nSCS: Serial chip select. A logic low on this pin enables serial interface communication. Internal pullup resistor.
  • SDI: Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pulldown resistor.
  • SDO: Serial data output. Data is shifted out on the rising edge of the SCLK pin. Push-pull output.
  • SCLK: Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
  • DRVOFF: Gate driver shutdown pin. Logic high to pull down both high-side and low-side gate driver outputs. Internal pull-down

    Resistor.

  • nSLEEP: Device enable pin. Logic low to shutdown the device and enter sleep mode. Internal pulldown resistor.
C

IPROPI/ PWM2 - Sense output is multiplexed from any of driver load current feedback, PVDD voltage feedback, or thermal cluster temperature feedback. Can also be configured as second PWM pin input for half-bridge drivers.

D SO - Shunt amplifier output.
E

Gate Driver, EC Driver, Heater Test points (Left to Right):

  • ECDRV - For EC control, pin controls the gate of external MOSFET for EC voltage regulation
  • GH_HS - Gate driver output for heater MOSFET. Connected to gate of high-side MOSFET
  • GH2 - High-side gate driver output. Connected to the gate of the high-side MOSFET.
  • GL2 - Low-side gate driver output. Connected to the gate of the low-side MOSFET
  • GL1- Low-side gate driver output. Connected to the gate of the low-side MOSFET
  • GH1 - High-side gate driver output. Connect to the gate of the high-side MOSFET
F Drain of external EC voltage regulation FET (Top to Bottom):
  • OUT11 - If jumper is set between OUT11 and EC FET Drain then OUT11 is the drain of the EC FET
  • EC FET Drain
  • PVDD - If jumper is set between PVDD and EC FET Drain, then PVDD is the drain of the EC FET