Aee |
XDS110 header between
MSP432E401Y and MSPM0G3507. |
B |
Main signal
header:
- GD_IN1: Half-bridge and H-bridge control input
1.
- GD_IN2: Half-bridge and H-bridge control input
2.
- PWM1:
PWM input 1 for regulation of all drivers except
electrochrome.
- nSCS:
Serial chip select. A logic low on this pin enables serial
interface communication. Internal pullup resistor.
- SDI:
Serial data input. Data is captured on the falling edge of
the SCLK pin. Internal pulldown resistor.
- SDO:
Serial data output. Data is shifted out on the rising edge
of the SCLK pin. Push-pull output.
- SCLK:
Serial clock input. Serial data is shifted out and captured
on the corresponding rising and falling edge on this
pin.
- DRVOFF: Gate driver shutdown pin. Logic high to pull
down both high-side and low-side gate driver outputs.
Internal pull-down
Resistor.
- nSLEEP: Device enable pin. Logic low to shutdown the
device and enter sleep mode. Internal pulldown
resistor.
|
C |
IPROPI/ PWM2
- Sense output is multiplexed from any of driver load
current feedback, PVDD voltage feedback, or thermal cluster
temperature feedback. Can also be configured as second PWM pin
input for half-bridge drivers.
|
D |
SO - Shunt
amplifier output. |
E |
Gate Driver, EC
Driver, Heater Test points (Left to Right):
- ECDRV
- For EC control, pin controls the gate of external MOSFET
for EC voltage regulation
- GH_HS
- Gate driver output for heater MOSFET. Connected to
gate of high-side MOSFET
- GH2 -
High-side gate driver output. Connected to the gate of the
high-side MOSFET.
- GL2 -
Low-side gate driver output. Connected to the gate of the
low-side MOSFET
- GL1-
Low-side gate driver output. Connected to the gate of the
low-side MOSFET
- GH1 -
High-side gate driver output. Connect to the gate of the
high-side MOSFET
|
F |
Drain of external EC
voltage regulation FET (Top to Bottom):
- OUT11
- If jumper is set between OUT11 and EC FET Drain
then OUT11 is the drain of the EC FET
- EC FET
Drain
- PVDD -
If jumper is set between PVDD and EC FET Drain, then PVDD is
the drain of the EC FET
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