SLVUD41 October   2024 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521940 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config
  7. 4Revision History

2.7 Over-Current Deglitch

This section describes the default settings for the over current deglitch. When any of these registers are set (value = 1b), it enabled the long-deglitch option for the corresponding rail.

Table 2-14 Over Current Deglitch
Register NameField NameValueDescription
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_BUCK10x0Deglitch duration for OverCurrent signals for BUCK1 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_BUCK20x0Deglitch duration for OverCurrent signals for BUCK2 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_BUCK30x0Deglitch duration for OverCurrent signals for BUCK3 (High-Side Overcurrent, Low-Side Overcurrent and Low-Side Reverse/Negative OverCurrent) is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_LDO10x0Deglitch duration for OverCurrent signals of LDO1 is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_LDO20x0Deglitch duration for OverCurrent signals of LDO2 is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_LDO30x0Deglitch duration for OverCurrent signals of LDO3 is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_LDO40x0Deglitch duration for OverCurrent signals of LDO4 is ~20us