SLVUD41 October   2024 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521940 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config
  7. 4Revision History

2.4.1 Power Sequence Settings - Slot assignments

Table 2-6 Power-UP Sequence Settings - Slot Assignments
Register NameField NameValueDescription
BUCK1BUCK1_SEQUENCE_SLOTBUCK1_SEQUENCE_ON_SLOT0x5slot 5
BUCK2BUCK2_SEQUENCE_SLOTBUCK2_SEQUENCE_ON_SLOT0x0slot 0
BUCK3BUCK3_SEQUENCE_SLOTBUCK3_SEQUENCE_ON_SLOT0x4slot 4
LDO1LDO1_SEQUENCE_SLOT LDO1_SEQUENCE_ON_SLOT0x2slot 2
LDO2LDO2_SEQUENCE_SLOT LDO2_SEQUENCE_ON_SLOT0x6slot 6
LDO3LDO3_SEQUENCE_SLOT LDO3_SEQUENCE_ON_SLOT0x2slot 2
LDO4LDO4_SEQUENCE_SLOT LDO4_SEQUENCE_ON_SLOT0x2slot 2
GPO1GPO1_SEQUENCE_SLOTGPO1_SEQUENCE_ON_SLOT0x2slot 2
GPO2GPO2_SEQUENCE_SLOTGPO2_SEQUENCE_ON_SLOT0x0slot 0
GPIOGPIO_SEQUENCE_SLOTGPIO_SEQUENCE_ON_SLOT0x0slot 0
nRSTOUTnRST_SEQUENCE_SLOT nRST_SEQUENCE_ON_SLOT0x9slot 9

Note: PMIC rails are turned ON during the power-up sequence if the corresponding EN bit on section "Enable Setting" is set to 0x01.

Table 2-7 Power-Down Sequence Settings - Slot Assignments
Register NameField NameValueDescription
BUCK1BUCK1_SEQUENCE_SLOTBUCK1_SEQUENCE_OFF_SLOT0x2slot 2
BUCK2BUCK2_SEQUENCE_SLOTBUCK2_SEQUENCE_OFF_SLOT0x4slot 4
BUCK3BUCK3_SEQUENCE_SLOTBUCK3_SEQUENCE_OFF_SLOT0x0slot 0
LDO1LDO1_SEQUENCE_SLOT LDO1_SEQUENCE_OFF_SLOT0x2slot 2
LDO2LDO2_SEQUENCE_SLOT LDO2_SEQUENCE_OFF_SLOT0x0slot 0
LDO3LDO3_SEQUENCE_SLOT LDO3_SEQUENCE_OFF_SLOT0x2slot 2
LDO4LDO4_SEQUENCE_SLOT LDO4_SEQUENCE_OFF_SLOT0x4slot 4
GPO1GPO1_SEQUENCE_SLOTGPO1_SEQUENCE_OFF_SLOT0x2slot 2
GPO2GPO2_SEQUENCE_SLOTGPO2_SEQUENCE_OFF_SLOT0x0slot 0
GPIOGPIO_SEQUENCE_SLOTGPIO_SEQUENCE_OFF_SLOT0x0slot 0
nRSTOUTnRST_SEQUENCE_SLOT nRST_SEQUENCE_OFF_SLOT0x0slot 0