SLVUD41 October   2024 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521940 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config
  7. 4Revision History

2.8 Mask Settings

This section describes the settings that are masked by default and the effect they have on the device state as well as the nINT pin.

Table 2-15 Mask Settings
Register NameField NameValueDescription
Mask effects on device state and nINT pinMASK_CONFIGMASK_EFFECT0x03no state change, nINT reaction, bit set for Faults
UV MaskINT_MASK_UVBUCK1_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVBUCK2_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVBUCK3_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVLDO1_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVLDO2_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVLDO3_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVLDO4_UV_MASK0x0un-masked (Faults reported)
Power-up retries/attemptsINT_MASK_UVMASK_RETRY_COUNT0x0Device does retry up to 2 times, then stay off
Die TemperatureMASK_CONFIGSENSOR_0_WARM_MASK0x0un-masked (Faults reported)
MASK_CONFIGSENSOR_1_WARM_MASK0x0un-masked (Faults reported)
MASK_CONFIGSENSOR_2_WARM_MASK0x0un-masked (Faults reported)
MASK_CONFIGSENSOR_3_WARM_MASK0x0un-masked (Faults reported)
Masking bit to control whether nINT pin is sensitive to PushButton (PB)MASK_CONFIGMASK_INT_FOR_PB0x1masked (nINT not sensitive to any PB events)
Masking bit to control whether nINT pin is sensitive to RV (Residual Voltage) MASK_CONFIGMASK_INT_FOR_RV0x0un-masked (nINT pulled low for any RV events during transition to ACTIVE state or during enabling of rails)