7.3.1 Lock Detect

The lock detect signal is generated in the phase frequency detector by comparing the VCO target phase against the VCO actual phase. When the two compared phase signals remain aligned for several clock cycles, an internal signal goes high. The precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged and compared against a reference voltage to generate the LD signal. The number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic behavior.

By default, the internal lock detect signal is made available on the LD pin. Register bits MUX_CTRL_n can be used to control a multiplexer to output other diagnostic signals on the LD output. The LD control signals are shown in Table 2. Table 3 shows the LD Control Signal Mode settings.

7.3.2 LO Divider

The LO divider is shown in Figure 66. It frequency divides the VCO output. Only one of the dividers operates at a time, and the appropriate output is selected by a mux. DIVn bits are controlled through LO_DIV_SEL_n. The output is buffered and provided on output pins LOn_OUT_P and LOn_OUT_N. Outputs are phase-locked but not phase-matched. The output level is controlled through BUFOUT_BIAS.

Figure 66. LO Divider

LO_DIV_IB determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should be disabled during normal operation.

7.3.3 Selecting the VCO and VCO Frequency Control

To achieve a broad frequency tuning range, the TRF3765 includes four VCOs. Each VCO is connected to a bank of coarse tuning capacitors that determine the valid operating frequency of each VCO. For any given frequency setting, the appropriate VCO and capacitor array must be selected.

The device contains logic that automatically selects the appropriate VCO and capacitor bank. Set bit EN_CAL to initiate the calibration algorithm. During the calibration process, the device selects a VCO and a tuning capacitor state such that V_TUNE matches the reference voltage set by VCO_CAL_REF_n. Accuracy of the resulting tuning word is increased through bits CAL_ACC_n at the expense of increased calibration time. A calibration begins immediately when EN_CAL is set; as a result, all registers must contain valid values before a calibration is initiated.

The calibration logic is driven by a CAL_CLK clock derived from the phase frequency detector frequency scaled according to the setting in CAL_CLK_SEL. Faster CAL_CLK frequencies enable faster calibrations, but the logic is limited to clock frequencies up to 600 kHz. The flag R_SAT_ERR is evaluated during the calibration process to indicate calibration counter overflow errors, which occur if CAL_CLK runs too quickly. If R_SAT_ERR is set during a calibration, the resulting calibration is not valid and CAL_CLK_SEL must be used to slow the CAL_CLK. CAL_CLK frequencies should not be set below 0.05 MHz. Reference clock frequency is usually limited by the calibration logic. f_REF × CAL_CLK_SEL scaling factor > 0.01 MHz and f_REF/(CAL_CLK_SEL scaling factor × f_PFD) < 8000 are required. For example, with f_REF = 61.44 MHz, f_PFD = 30.72 MHz and CAL_CLK_SEL at 1/128, 61.44/128 = 0.5 > 0.01 and 61.44/(30.72 × 1/128) = 256 < 8000.

When VCOSEL_MODE is 0, the device automatically selects both the VCO and capacitor bank within 46 CAL_CLK cycles. When VCOSEL_MODE is 1, the device uses the VCO selected in VCO_SEL_0 and VCO_SEL_1 and automatically selects the capacitor array within 34 CAL_CLK cycles. The VCO and capacitor array settings that result from a calibration cannot be read from the VCO_SEL_n and VCO_TRIM_n bits in Registers 2 and 7. These settings can only be read from Register 0.

Automatic calibration can be disabled by setting CAL_BYPASS to 1. In this manual calibration mode, the VCO is selected through register bits VCO_SEL_n, while the capacitor array is selected through register bits VCO_TRIM_n. Calibration modes are summarized in Table 4. After calibration is complete, the PLL is released from calibration mode and reaches phase lock.

During the calibration process, the TRF3765 scans through many frequencies. RF and LO outputs should be disabled until calibration is complete. At power-up, the RF and LO output are disabled by default. Once a calibration has been performed at a given frequency setting, the calibration remains valid over all operating temperature conditions.

7.3.4 External VCO

An external LO or VCO signal may be applied. EN_EXTVCO powers the input buffer and selects the buffered external signal instead of an internal VCO. Dividers, phase-frequency detector, and charge pump remain enabled and may be used to control V_TUNE or an external VCO. NEG_VCO must correspond to the sign of the external VCO tuning characteristic. EXT_VCO_CTRL = 1 asserts a logic 1 output level at the corresponding output pin. This configuration can be used to enable or disable the external VCO circuit or module.

7.4.1 VCO_TEST_MODE

Setting VCO_TEST_MODE forces the currently selected VCO to the edge of its frequency range by disconnecting the charge pump input from the phase detector and loop filter, and forcing its output high or low. The upper or lower edge of the VCO range is selected through COUNT_MODE_MUX_SEL.

VCO_TEST_MODE also reports the value of a frequency counter in COUNT, which can be read back in Register 0. COUNT reports the number of digital N divider cycles in the PLL, directly related to the period of f_N, that occur during each CAL_CLK cycle. Counter operation is initiated through the bit EN_CAL. Table 5 summarizes the settings for VCO_TEST_MODE.

7.4.2 Readback Mode

Register 0 functions as a readback register. The TRF3765 implements the capability to read back the content of any serial programming interface register by initializing Register 0.

Each read-back operation consists of two phases: a write followed by the actual reading of the internal data. This sequence is described in the timing diagram (see Figure 2). During the write phase, a command is sent to TRF3765 Register 0 to set it to readback mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data are transferred to the READBACK pin where it can be read at the following falling edge (LSB first). The first clock after the latch enable STROBE, pin 5, goes high (that is, the end of the write cycle) is idle and the following 32 clock pulses transfer the internal register contents to the READBACK pin (pin 6).

7.4.3 Integer and Fractional Mode Selection

The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO) frequency is an integer multiple of the phase frequency detector (PFD) frequency, f_PFD, then Integer mode can be selected. The normalized in-band phase noise floor in Integer mode is lower than in Fractional mode. In Integer mode, the feedback divider is an exact integer, and the fraction is zero. While operating in Integer mode, the register bits corresponding to the fractional control are don’t care.

In Fractional mode, the feedback divider fractional portion is non-zero on average. With 25-bit fractional resolution, RF stepsize f_PFD/2²⁵ is less than 1 Hz with a f_PFD up to 33 MHz. The appropriate fractional control bits in the serial register must be programmed.

7.4.4 PLL Architecture

Figure 67 shows a diagram of the PLL loop.

Figure 67. PLL Architecture

The output frequency is given by Equation 1:

Equation 1.

The rate at which phase comparison occurs is f_REF/RDIV. In Integer mode, the fractional setting is ignored and Equation 2 is applied.

Equation 2.

The feedback divider block consists of a programmable RF divider, a prescaler divider, and an NF divider. The prescaler can be programmed as either a 4/5 or an 8/9 prescaler. The NF divider includes an A counter and an M counter.

7.4.5 Fractional Mode Setup

Optimal operation of the PLL in Fractional mode requires several additional register settings. Recommended values are listed in Register Maps. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK, and ISOURCE_TRIM values according to the chosen frequency band.

7.5.1 PLL 4WI Registers

7.5.2 Readback from the Internal Register Banks

The TRF3765 integrates eight registers: Register 0 (000) to Register 7 (111). Registers 1 through 6 are used to set up and control the TRF3765 functions, Register 7 is used for factory functions, and Register 0 is used for the readback function, as shown in Readback Mode.

Register 0 must be programmed with a specific command that sets the TRF3765 into readback mode and specifies the register to be read, according to the following parameters:

• Set B[31] to 1 to put TRF3765 into readback mode.
• Set B[30,28] equal to the address of the register to be read (000 to 111).
• Set B27 to control the VCO frequency counter in VCO test mode.