SLWU067D November 2009 – March 2022 ADS4122 , ADS4125 , ADS4126 , ADS4128 , ADS4129 , ADS4142 , ADS4145 , ADS4146 , ADS4149 , ADS41B25 , ADS41B29 , ADS41B49 , ADS58B18 , ADS58B19
Option 3 is used for a differential LVPECL clock. This configuration eliminates the need for a crystal filter. It uses the same EEPROM configuration as Option 2, but in this case, the ADC clock pins are connected to Y1N and Y1P. The jumper setting uses the clock output Y1P and Y1N from CDCE72010, to clock ADC. This configuration is not recommended for SNR critical applications. Notice that the clock frequency does not change. The frequency remains the same as in Clock Option 2. The test result using this option is shown in Figure 2-4.