SLWU067D November 2009 – March 2022 ADS4122 , ADS4125 , ADS4126 , ADS4128 , ADS4129 , ADS4142 , ADS4145 , ADS4146 , ADS4149 , ADS41B25 , ADS41B29 , ADS41B49 , ADS58B18 , ADS58B19
Power is supplied to the EVM through banana jacks; from this input power, three different ways are available of delivering power to the ADC and the other EVM functions . Figure 2-3 shows a simplified representation of the power options available for the ADS41xx/58B18EVM. The default option is to provide 3.3 V to the red banana jack J16, and from there the EVM generates 1.8 V for the analog and digital supplies to the ADC. The 1.8-V rails for the ADC can be generated from the 3.3-V input either through a low-noise dropout regulator (TPS79618), from a switching regulator (TPS62562) for maximum power efficiency or from an external 1.8-V power supply. The EVM also generates the proper voltages for optional features of the EVM such as the Clock Generation circuitry, the USB circuitry, and the CMOS output buffer.
Some ADC devices that may be evaluated on the ADS41xx/58B18 platform require a 3.3-V supply for an internal front-end buffer. For this reason, an isolated 3.3V_BUF supply is on the power section of the schematic.
Power for the optional THS4509 operational amplifier is supplied by banana jacks J9 and J11. If the amplifier is being evaluated, 5 V is supplied to J9 and J11 is connected to ground. Otherwise, these inputs may be left unconnected.
The power supply for the default operation of the ADS41xx/58B18EVM has been simplified by requiring only a single 3.3 V. Table 2-1 displays the general jumper setting information; Table 2-2 displays the various power option settings. Prior to making any jumper settings, see the schematic located on the TI Web site in the relevant ADS41xx or ADS41Bxx product folder.
EVM Banana Jack/Jumper | Description | Jumper setting |
---|---|---|
J16 | Input | 3.3-V power supply input |
JP3 | 3.3 V for CDCE72010 | Shunt for CDCE72010 operation |
JP13 | 1.8-VA input | 1-2 → 1.8 V from LDO/switching regular to 1.8 VA of ADC (default); 2-3 → option for external 1.8-V supply |
JP14 | 1.8-VD input | 1-2 → 1.8 V from LDO/switching regular to 1.8 VD of ADC (default); 2-3 → option for external 1.8-V supply |
JP17 | 3.3-V input selection for LDO/switching regulator | 1-2 → 3.3-V input for TPS62562 (default); 2-3 → 3.3-V input for TPS79618 |
JP19 | 1.8-V selection from LDO/switching regulator | 1-2 → 1.8-V output from TPS62562 (default); 2-3 → 1.8-V output from TPS79618 |
EVM Option | Evaluation Goal | Jumper Changes Required | Voltage on J16 | Comments |
---|---|---|---|---|
1 | Evaluate ADC performance using a switching power supply (TP62562) | JP13 → 1-2; JP14 → 1-2; JP17 → 1-2; JP19 → 1-2; | 3.3 V | Maximum performance and efficiency. |
2 | Evaluate ADC performance using a LDO-based (TPS79618) solution. | JP13 → 1-2; JP14 → 1-2; JP17 → 2-3; JP19 → 2-3; | 3.3 V | Maximum performance. |
3 | Evaluate ADC performance using an isolated ADC AVDD and DVDD for current consumption measurements | JP13 → 1.8V on 2-3; JP14 → 1.8V on 2-3; JP17 → open3; JP19 → open; | 3.3 V | Isolated power supply for current consumption measurements |