SLWU067D November   2009  – March 2022 ADS4122 , ADS4125 , ADS4126 , ADS4128 , ADS4129 , ADS4142 , ADS4145 , ADS4146 , ADS4149 , ADS41B25 , ADS41B29 , ADS41B49 , ADS58B18 , ADS58B19

 

  1.   Trademarks
  2. 1Overview
    1. 1.1 Purpose
    2. 1.2 EVM Quick-Start Procedure
  3. 2Circuit Description
    1. 2.1 Schematic Diagram
    2. 2.2 Circuit Function
      1. 2.2.1 Power
        1. 2.2.1.1 Power Supply Option 1
        2. 2.2.1.2 Power Supply Option 2
        3. 2.2.1.3 Power Supply Option 3
      2. 2.2.2 Clock Input
        1. 2.2.2.1 Clock Option 1
        2. 2.2.2.2 Clock Option 2
        3. 2.2.2.3 Clock Option 3
      3. 2.2.3 Analog Inputs
        1. 2.2.3.1 Analog Input Option 1
        2. 2.2.3.2 Analog Input Option 2
      4. 2.2.4 Digital Outputs
  4. 3TI ADC SPI Control Interface
    1. 3.1 Installing the ADC SPI Interface
    2. 3.2 Setting Up the EVM for ADC SPI Control
    3. 3.3 Using the TI ADC SPI Interface Software
      1. 3.3.1 SPI Register Writes
  5. 4Quick Start Setup
  6. 5Evaluation
    1. 5.1 Register Programming
    2. 5.2 Quick-Test Results

2.2.2 Clock Input

The clock can be supplied to the ADC in several ways. The default clocking option is to supply a single-ended clock directly to the SMA connecter, J19, directly. This clock is converted to differential and AC coupled to the ADC by transformer coupling. The clock input must be from a clean, low-jitter source and is commonly filtered external to the board by a narrow bandpass filter. The clock amplitude is commonly set to about 1.5 V peak-to-peak, and the amplitude offset is not an issue due to the AC coupling of the clock input. The clock source is commonly synchronized with the signal generator of the input frequency to keep the clock and IF coherent for meaningful FFT analysis.

Alternatively, the clock may be supplied by an onboard VCXO and CDCE72010 clock buffer. The CDCE72010 clock buffer has been factory programmed to output a clock to the ADC that is 1/4 the rate of the onboard VCXO. While using this clock option, a separate 20-MHz reference clock must be supplied to the CDCE72010 by way of the clock input SMA connector J19. From the CDCE72010, two clocking options to the ADC are possible. A differential LVPECL clock output may be connected to the ADC clock input or a single-ended CMOS clock from the CDCE72010 may be routed to the ADC transformer-coupled clock input through an onboard crystal filter. For better performance, selecting the CMOS clock through a crystal output is recommended. Prior to making any jumper settings and resistor changes, see the schematic located on the TI Web site in the relevant ADS41xx or ADS41Bxx product folder. Table 2-4 displays the various clock option settings. The VCXO and crystal filter do not come populated on the EVM by default, although the CDCE72010 clock buffer is installed.

Table 2-3 Clock Input Jumper Description
EVM Jumper OptionsDescriptionJumper Setting
JP4ENABLE VCXO1 TC0-21111-2 → VCXO enabled 2-3 → VCXO disabled
J19SMA connector for clock input
JP1CDCE72010 power down1-2 → CDCE72010 is power down; Open → CDCE72010 is on
JP2CDCE72010 reset1-2 → Reset , Open → Normal operation. (default)
R81/107Clock In or CDC ref. jumperR81 → J19 supplies clock directly to ADC; R107 → Reference clock for CDCE72010
R113/114/115Clock input to +ve terminal of T4 for ADC clockR115 → Connects J19 to ADC; R114 → Connects Y0 output of CDCE72010 (This path has crystal filter) to ADC; R113 → Connects Y1P (Differential LVPECL clock output of CDCE72010) to ADC
R108/110Clock input to -ve terminal of T4 for ADC clockR110→ Connects to ground (Default); R108→ Connects to Y1N (Differential clock output of CDCE72010) only to be used with Y1P.
JP8Mode select pin for CDCE720101-2 → High (default), see data sheet of CDCE72010; 2-3 → Ground
R111/112PLLOCK LEDR111 → Connects to D3 diode; R112 → Ground through 10-nF capacitor
JP10Aux_sel pin for CDCE720101-2 → High, see data sheet of CDCE72010; 2-3 → Ground (Default)
Table 2-4 EVM Clock Input Options
EVM OptionsEvaluation GoalJumper and Resistor Changes RequiredFrequency Input on J19CDC Configuration DescriptionComments
1Evaluate ADC performance using a sinusoid clockJP1 → 1-2; JP2 → no shunt; JP4 → 2-3; Install: R81, R110, R115ADC's Sampling FrequencyNADefault
2Evaluate ADC performance using a crystal filtered LVCMOS clock derived from CDCE72010JP1 → no shunt; JP2 → no shunt; JP4 → 1-2; Install: R107, R110, R114; Remove: R81, R11520M for VCXO@983.04 MHzDivide VCXO frequency by 4, output on Y0Maximum performance
3Evaluate ADC performance using a differential LVPECL clockJP1 → no shunt; JP2 → no shunt; JP4 → 1-2; Install: R107, R108, R114; Remove: R81, R110, R11520M for VCXO@983.04 MHzDivide VCXO frequency by 4, differential LVPECL Clock output on Y1P and Y1NNot recommended for most applications