SLWU087E november 2013 – june 2023
The TI TSW14J57 EVM is a pattern generator and data capture card with a JESD204B serial interface. The TSW14J57 has an FMC+ connector that can be used to evaluate the performance of the TI JESD204B device family ADCs and DACs (see Figure 7-1). For an ADC, the high speed serial data is captured and de-serialized and formatted by an Intel PSG®Arria® 10 FPGA, then stored in an onboard DDR4 SDRAM, allowing the TSW14J57 to store up to 1G of 16-bit samples. It also supports lane speeds from 2 Gbps to 15 Gbps, from 1 to 16 lanes with one firmware build. Together with the accompanying HSDC Pro GUI, it is a complete system that captures and evaluates data samples from ADC EVMs and generates and sends desired test patterns to DAC EVMs.
To acquire data on a host PC, the FPGA reads the data from memory and transmits it on SPI. An onboard high-speed USB-to-SPI converter bridges the FPGA SPI interface to the host PC and GUI.
In Pattern Generator Mode, the TSW14J57 generates desired test patterns for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the TSW14J57. The FPGA stores the data received into the board DDR4 memory module. The data from the memory is then read by the FPGA and transmitted to a DAC EVM across the JESD204B interface connector.
In the Instrument Options tab of the GUI, the option called "Dynamic Configuration" allows the user to change certain JESD204B parameters without loading new firmware into the FPGA. The ini files load default values for these parameters based on what ADC or DAC is selected and what mode of operation is chosen. For the most part, users should not have to change these values in this tab. If any values are changed, the default values of the ini file will be overwritten. Any changes will effect the operation of the JESD204B interface and will have to be made at both the receiver and transmit side of the interface.