SLWU087E november 2013 – june 2023
If opening the GUI for the first time, when setting up for pattern generator mode, make sure “DAC” in the top right side of the GUI is selected. After clicking on “DAC”, the top level GUI shall look as shown in Figure 5-2.
To run the GUI in DAC pattern generator mode, the FPGA must be loaded with the proper firmware, which is determined by the DAC type to be tested.
In the “Select DAC” button of the GUI, click on the drop down arrow and select the DAC3152 (Figure 5-3). This will be the targeted EVM for this test example.
Click on “Yes” when asked “Do you want to update the firmware for DAC”. The firmware for this setup will now be loaded during this process, which will take approximately 20 seconds. After the firmware load has completed, the LED’s labeled USER_LED (0–7) will now turn on except for USER_LED 3 and 5. USER_LED 3 is used to indicate the status of a second PLL, which is not used with this firmware build, and USER_LED 5 indicates if there is a FIFO overflow (error) of the transmit data.
If the TSW1400 is not receiving a valid clock from the DAC EVM, USER_LED3 and USER_LED4 will be off.