SLWU087E november   2013  – june 2023

 

  1.   1
  2.   High Speed Data Converter Pro GUI
  3.   Trademarks
  4. Introduction
  5. Software Start up
    1. 2.1 Installation Instructions
    2. 2.2 USB Interface and Drivers
    3. 2.3 Device ini Files
  6. User Interface
    1. 3.1 Toolbar
      1. 3.1.1 File Options
        1. 3.1.1.1 User Profiles
        2. 3.1.1.2 Resize Window
      2. 3.1.2 Instrument Options
        1. 3.1.2.1 TSW14J56 and High Speed Data Converter (HSDC) Pro Eye Quality Analysis
        2. 3.1.2.2 IO Delay
        3. 3.1.2.3 JESD204B Error Injection
        4. 3.1.2.4 FPGA Registers Write Read
      3. 3.1.3 Data Capture Option
        1. 3.1.3.1 Capture Option
        2. 3.1.3.2 Trigger Option
        3. 3.1.3.3 Using Multiple TSW14xxx and ADC EVM’s for Simultaneous Capture using Trigger Option
          1. 3.1.3.3.1 Hardware Setup
          2. 3.1.3.3.2 Setting up the Slave Board
          3. 3.1.3.3.3 Setting up the Master Board
          4. 3.1.3.3.4 Read Captured Memory from the Slave Board
      4. 3.1.4 Test Options
        1. 3.1.4.1  Notch Frequency Bins
        2. 3.1.4.2  2 Channel Display and Cursor Lock
        3. 3.1.4.3  Analysis Window Markers
        4. 3.1.4.4  X-Scale in Time
        5. 3.1.4.5  Y-Scale in Voltage
        6. 3.1.4.6  Other Frequency Options
        7. 3.1.4.7  NSD Marker
        8. 3.1.4.8  Phase Plot
        9. 3.1.4.9  Phase in Degree
        10. 3.1.4.10 Histogram
        11. 3.1.4.11 Disable User Popups
        12. 3.1.4.12 HSDC Pro Lite Version
      5. 3.1.5 Help
    2. 3.2 Status Windows
    3. 3.3 Mode Selection
    4. 3.4 Device Selection
    5. 3.5 Skip Configuration
    6. 3.6 Capture Button (ADC Mode Only)
    7. 3.7 Test Selection (ADC Mode only)
      1. 3.7.1 Single Tone FFT
        1. 3.7.1.1 Parameter Controls
        2. 3.7.1.2 ADC Captured Data Display Pane
        3. 3.7.1.3 FFT Power Spectrum
        4. 3.7.1.4 Overlay Unwrap Waveform
        5. 3.7.1.5 Single Tone FFT Statistics
      2. 3.7.2 Multi Channel Display
      3. 3.7.3 Unit Selection
      4. 3.7.4 Time Domain
      5. 3.7.5 Two Tone
      6. 3.7.6 Channel Power
    8. 3.8 DAC Display Panel (DAC Mode only)
      1. 3.8.1 Send Button (DAC Mode Only)
      2. 3.8.2 Load File to Transfer into TSW14xxx Button
      3. 3.8.3 Parameter Controls
    9. 3.9 I/Q Multi-Tone Generator
  7. ADC Data Capture Software Operation
    1. 4.1 Testing a TSW1400 EVM with an ADS5281 EVM
    2. 4.2 Testing a TSW1400EVM with an ADS62P49EVM (CMOS Interface)
  8. TSW1400 Pattern Generator Operation
    1. 5.1 Testing a TSW1400 EVM with a DAC3152 EVM
    2. 5.2 Loading DAC Firmware
    3. 5.3 Configuring TSW1400 for Pattern Generation
    4. 5.4 Testing a TSW1400 EVM with a DAC5688EVM (CMOS Interface)
  9. TSW14J58 Functional Description
    1. 6.1 Testing the TSW14J58 EVM with an ADC12DJ3200 EVM
  10. TSW14J57 Functional Description
    1. 7.1 Testing the TSW14J57 EVM with an ADC34J45 EVM
  11. TSW14J56 Functional Description
    1. 8.1 Testing the TSW14J56 EVM with an ADC34J45 EVM
  12. TSW14J50 Functional Description
    1. 9.1 Device Selection
  13. 10TSW14J10 Functional Description
    1. 10.1 DAC and ADC GUI Configuration File Changes When Using a Xilinx Development Platform
    2. 10.2 DAC38J84EVM GUI Setup Example
  14.   A Signal Processing in High Speed Data Converter Pro
    1.     A.1 Introduction
    2.     A.2 FFT Calculation from Time Domain Data
      1.      A.2.1 FFT Window Correction Factor
    3.     A.3 FFT Filtering
    4.     A.4 Single Tone Parameters
      1.      A.4.1 Number of Neighboring Bins for each FFT Window
    5.     A.5 Fundamental Power
      1.      A.5.1 Harmonic Distortions
      2.      A.5.2 SNR
      3.      A.5.3 SFDR
      4.      A.5.4 THD
      5.      A.5.5 SINAD
      6.      A.5.6 ENOB
      7.      A.5.7 Next Spur
    6.     A.6 Two Tone Parameters
    7.     A.7 Average FFT Calculation
    8.     A.8 NSD Calculation
  15.   B History Notes
  16.   C Revision History

Trigger Option

Clicking on the Trigger Option will open a new panel as shown in Figure 3-10. This option is not available for the TSW1405/06. The GUI provides four options of capturing data using a trigger function. Selecting Trigger mode enable will arm the TSW14xxx to accept an external trigger.

GUID-20210511-CA0I-JLHN-9RZW-TBZX0VKDRC6X-low.pngFigure 3-10 Trigger Option

With both enables selected, the capture button on the main panel of the GUI now changes from "Capture" to “Generate Trigger”. When the user clicks on this button, the GUI sends a CMOS logic level (1.8 VDC) active high pulse to the four SMA connectors labeled SYNC1, SYNC2, SYNC3, and SYNC4 on the TSW1400. On the TSW14J5x, these are labeled as TRIG_OUT_A, TRIG_OUT_B, and TRIG_OUT_C. This signal can be used to trigger other TSW14xxx EVMs or the same TSW14xxx. To use this rising edge to trigger the same TSW14xxx, the user must connect a cable from the SMA labeled as “EXT_TRG_INPUT” SMA (J11) on the TSW1400 ("TRIG_IN", SMA J13 on the TSW14J5x) to one of the SYNC (TRG_OUT) SMA's. Without this connection, the GUI never detects a trigger and reports “No trigger occurred” a short time after the user has clicked on the "Generate Trigger" button. Once a trigger is detected, the GUI will do a capture.

Another trigger option is to use an external trigger source. To use this mode, only select “Trigger mode enable”. When this mode is selected, the status button located at the bottom of the main GUI screen will display “TRIGGER ARMED” in yellow and the capture button will display “Read DDR Memory”. The software is now waiting for a CMOS logic low to high transition to occur on the “EXT_TRG_INPUT” (TRG_IN) input SMA. Once this occurs, a data capture will occur. The user will now click on the “Read DDR Memory” button to display the captured data. If the user clicks on this button before a trigger occurred, a short time later a “No trigger occurred” message appears. If the external trigger is a continuous event, the GUI will not do a new capture until the user clicks on "Read DDR Memory". This causes the software to display the results from the first trigger event and reload the memory with new data on the next rising edge of the external trigger input.

Another trigger option involves selecting both "Trigger mode enable" and "Arm on next capture button press". With these two selected, the software will do a capture on the next rising edge detected on EXT_TRG_INPUT/TRIG_IN connectors only after the user clicks on the "capture" button. This mode comes in handy if there are multiple trigger pulses arriving but the user does not want to trigger until a certain time later. If a trigger is not detected within about 12 seconds after clicking on capture, the software will time out and report no trigger detected.

When using the trigger capture mode, the user has an option to capture data a fixed amount of samples after the capture has actually started. This is useful for devices that have a “High Resolution Burst mode”, where it takes several clock cycles to occur before valid samples are available. This delay is determined by the value entered in the “Trigger CLK Delays” box. The default value is “0”. The user can enter a value from 0–7 with the corresponding sample delay shown in Table 3-1. Note that the delay is also based on the number of channels captured. For example, if a user selects a Trigger Delay of “2” and is capturing data from 2 Channels, after a trigger is detected by the GUI, the data capture starts. With this delay setting though, the first data sample used by the GUI will be the 81th sample from the ADC after the trigger occurred.

Another trigger option involves selecting both “Trigger mode enable” and “Auto Re-Arm Trigger”. With these two selected, the TSW14xxx EVM captures the configured amount of samples (“# of samples per channel”, from the Capture Option). For every trigger pulse, (CMOS logic low to high transition that occurs on the “EXT_TRG_INPUT” (TRIG_IN, TSW14J5x) SMA.) and accumulate the captured samples in the DDR memory until the defined numbers of “Number of Triggers” is completed.

When using this capture mode, the status button located at the bottom of the main GUI screen displays “TRIGGER ARMED” in yellow and the capture button displays “Show Trigger Status”. Clicking on the “Show Trigger Status” button opens up a popup window displaying the status of the trigger operations with “Number of Triggers Occurred” and “% of DDR Filled”. Clicking on the “Stop and Exit” button stops the current capture operations without reading the captured sample. Clicking on the “Stop and Read the DDR Memory” button stops the current capture operations and read the captured samples from the DDR. After the configured Number of Triggers occurs and required amount of DDR gets filled, the “Stop and Read the DDR Memory” button displays “Read DDR Memory” and clicking on the same reads the captured samples from the DDR.

GUID-20210414-CA0I-5CSL-LL59-3ZNCTJC0PXKL-low.pngFigure 3-11 Auto Re-Arm Trigger Status Window

For DAC mode, with both enables selected, the send button on the main panel of the GUI now changes from "Send" to “Generate Trigger”. When this button is clicked, the GUI sends a CMOS logic high level (3 VDC) to the four SYNC SMAs on the TSW1400 and the three TRIG_OUT SMAs on the TSW14J5x. This signal can trigger other TSW14xxx EVMs or the same TSW14xxx. A cable must be connected from the “EXT_TRG_INPUT” (TRIG_IN, TSW14J5x) SMA to one of the SYNC (TRIG_OUT, TSW14J5x) SMAs to use this rising edge to trigger the same TSW14xxx. Without this connection, the GUI never sends the data from the memory.

Table 3-1 Trigger Delay Options
Trigger DelayNumber of Samples Skipped Per Channel
1 Channel2 Channel4 Channel8 Channel
180402010
2160804020
32401206030
43201608040
540020010050
648024012060
756028014070

Another trigger option involves selecting both “Trigger mode enable” and “Auto Re-Arm Trigger”. With these two selected the TSW14xxx EVM captures the configured amount of samples (“# of samples per channel”, from the Capture Option) for every trigger pulse (CMOS logic low to high transition that occurs on the “EXT_TRG_INPUT” (TRIG_IN, TSW14J5x) SMA.) and accumulate the captured samples in the DDR memory until the defined numbers of “Number of Triggers” is completed.

When using this capture mode, the status button located at the bottom of the main GUI screen displays “TRIGGER ARMED” in yellow and the capture button displays “Show Trigger Status”. Clicking on the “Show Trigger Status” button opens up a popup window displaying the status of the trigger operations with “Number of Triggers Occurred” and “% of DDR Filled”. Clicking on the “Stop and Exit” button stops the current capture operations without reading the captured sample. Clicking on the “Stop and Read the DDR Memory” button stops the current capture operations and read the captured samples from the DDR. After the configured Number of Triggers occurs and required amount of DDR gets filled, the “Stop and Read the DDR Memory” button displays “Read DDR Memory” and clicking on the same reads the captured samples from the DDR.

For DAC Auto Re-Arm Trigger mode, when the board receives a trigger signal at “EXT_TRG_INPUT” (TRIG_IN, TSW14J5x) SMA, the samples from the start index is sent out to the DAC from the FPGA.