This section describes the pattern generator operation when testing with a DAC3152 EVM that has a LVDS input interface.
- Power down the TSW1400.
- Connect J5 of the DAC3152 to connector J4 of the TSW1400.
- Provide +5 VDC to J12 and return to J13 of the DAC3152 EVM.
- Provide a 0.5-Vrms 250-MHz clock to J9 of the DAC3152 EVM.
- Power up the TSW1400 EVM
- Start up the HSDC Pro GUI as described in the Software Start Up.
- A TSW1400 EVM connected to a DAC3152 EVM is shown in Figure 5-1.
Note: The FPGA clocks from DAC EVMs to the TSW1400 EVM
have to be LVDS level. Exceeding LVDS levels may damage the TSW1400 FPGA.