SLWU095 april 2023
The TSW14J59 has 5 SMA connectors. Table 3-4 defines the connectors:
Component | Connector | Description |
---|---|---|
J31 | SYNCA | 3.3V or 1.8V CMOS logic SYNC output from FPGA pin F22. A shunt on pins 1–2 of J21 sets the level to 3.3V (default). A shunt on pins 2-3 sets the level to 1.8V. |
J32 | SYNCB | 3.3V or 1.8V CMOS logic SYNC output from FPGA pin G22. A shunt on pins 1–2 of J21 sets the level to 3.3V (default). A shunt on pins 2-3 sets the level to 1.8V. |
J33 | SYNCC | 3.3V or 1.8V CMOS logic SYNC output from FPGA pin M24. A shunt on pins 1–2 of J21 sets the level to 3.3V (default). A shunt on pins 2-3 sets the level to 1.8V. |
J36 | TRIG IN A | 3.3V or 1.8V CMOS logic trigger input to FPGA pin E26. A shunt on pins 1–2 of J21 sets the level to 3.3V (default). A shunt on pins 2-3 sets the level to 1.8V. |
J43 | TRIG IN B | 3.3V or 1.8V CMOS logic trigger input to FPGA pin L23. A shunt on pins 1-2 of J21 sets the level to 3.3V (default). A shunt on pins 2-3 sets the level to 1.8V. |