SLWU095 april   2023

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Functionality
    1. 2.1 ADC EVM Data Capture
    2. 2.2 DAC EVM Pattern Generator
  5. 3Hardware Configuration
    1. 3.1 Power Connections
    2. 3.2 Switches, Jumpers, and LEDs
      1. 3.2.1 Switches and Push-Buttons
      2. 3.2.2 Jumpers
    3. 3.3 LEDs
      1. 3.3.1 Power and Configuration LEDs
      2. 3.3.2 Spare LEDs
      3. 3.3.3 Connectors
        1. 3.3.3.1 SMA Connectors
        2. 3.3.3.2 FPGA Mezzanine Card (FMC+) Connector
        3. 3.3.3.3 JTAG Connectors
        4. 3.3.3.4 USB3.0 I/O Connection
  6. 4Software Start-Up
    1. 4.1 Installation Instructions
    2. 4.2 USB Interface and Drivers
  7. 5Downloading Firmware

2.2 DAC EVM Pattern Generator

In pattern generator mode, the TSW14J59EVM generates desired test patterns for DAC EVMs under test. These patterns are sent from the host PC over the USB interface to the TSW14J59. The FPGA stores the data received into the on-board DDR4 memory. The data from the memory is then read by the FPGA, converted to JESD204C_B serial format, then transmitted to a DAC EVM. The TSW14J59 can generate patterns up to 1.536G 16-bit samples at a line rate up to 32Gbps.

The HSDC Pro GUI comes with several existing test patterns that can be download immediately. Like the ADC capture mode, the DAC pattern generator mode uses information from the .csv file to load predetermined JESD204C_B interface information to the FPGA.