SLWU095 april   2023

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Functionality
    1. 2.1 ADC EVM Data Capture
    2. 2.2 DAC EVM Pattern Generator
  5. 3Hardware Configuration
    1. 3.1 Power Connections
    2. 3.2 Switches, Jumpers, and LEDs
      1. 3.2.1 Switches and Push-Buttons
      2. 3.2.2 Jumpers
    3. 3.3 LEDs
      1. 3.3.1 Power and Configuration LEDs
      2. 3.3.2 Spare LEDs
      3. 3.3.3 Connectors
        1. 3.3.3.1 SMA Connectors
        2. 3.3.3.2 FPGA Mezzanine Card (FMC+) Connector
        3. 3.3.3.3 JTAG Connectors
        4. 3.3.3.4 USB3.0 I/O Connection
  6. 4Software Start-Up
    1. 4.1 Installation Instructions
    2. 4.2 USB Interface and Drivers
  7. 5Downloading Firmware

3.3.3.4 USB3.0 I/O Connection

Control of the TSW14J59EVM is through the USB 3.0 connector J9 and a Cypress FX3 USB3.0 Controller. This provides the interface between the HSDC Pro GUI running on a PC using the Microsoft®Windows® operating system and the FPGA. This provides a high speed 32 bit parallel data interface between the USB3.0 controller and the FPGA.

For the computer, the drivers needed to access the USB port are included on the HSDC Pro GUI installation software that can be downloaded from the web. The drivers are automatically installed during the installation process. On the TSW14J59EVM, the USB3.0 port is used to identify the type and serial number of the EVM under test, load the desired FPGA configuration file, capture data from ADC EVMs, and send test pattern data to the DAC EVMs.

Power Monitor PMBUS Connector: The power monitor device, UCD90120A, is programmed though header J48. Using the TI Fusion GUI, the user can program the device and monitor all power rails used by the TSW14J59EVM. This interface also allows the user to monitor the status of the FPGA core power supply U1, TI part number TPS40428.