SLYA042 July   2024 FDC1004 , FDC1004-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 CSAs and Input Bias Stage
  6. 3 CSA and Gain Error Factor
  7. 4 Applications for Resistance at Input Pins of Current Sense Amplifiers
    1. 4.1 Input Resistance Design Considerations
  8. 5 Applications for Input Resistance at Reference Pins of Current Sense Amplifiers
    1. 5.1 Bidirectional CSA and Applications
    2. 5.2 Driving CSA Reference Pin With High-Resistance Source Voltage
    3. 5.3 Input Resistance at Reference Pin Design Considerations
  9. 6 Design Procedure and Error Calculation for External Input Resistance on CSA
    1. 6.1 Calculating eEXT for INA185A4 With 110Ω Input Resistors
  10. 7 Design Procedure for Input Resistance on Capacitively-Coupled Current Sense Amplifier
    1. 7.1 Bench Verification of Input eEXT for Capacitively-Coupled Current Sense Amplifiers
  11. 8 Design Procedure for Input Resistance at CSA Reference Pins
  12. 9 Input Resistance Error Test with INA185 Over Temperature
    1. 9.1 Schematic
    2. 9.2 Methods
    3. 9.3 Theoretical Model
    4. 9.4 Data for INA185A4 with 110Ω Input Resistors
      1. 9.4.1 Data Calculations
    5. 9.5 Analysis
  13. 10Input Resistance Error Test with INA191 Over Temperature
    1. 10.1 Schematic
    2. 10.2 Methods
    3. 10.3 Theoretical Model
    4. 10.4 Data for INA191A4 With 2.2kΩ Input Resistors
      1. 10.4.1 Data Analysis
    5. 10.5 Analysis
  14. 11Derivation of VOS, EXT for a Single Stage Current Sense Amplifier (CSA)
  15. 12Summary
  16. 13References

5.3 Input Resistance at Reference Pin Design Considerations

Whenever using large input resistance (>10-Ω) at CSA reference pins, the system engineer can follow Section 8 and make following considerations:

  1. Is the reduced dynamic range large enough for required system dynamic range?
  2. If ADC must be single-ended, can system perform 1-point offset calibration to negate VREF tolerance and CSA input offset?
  3. Can ADC make a differential/pseudo-differential measurement to negate VREF variation without need for 1-point calibration?
    1. Furthermore, can differential ADC and system perform a 1-point calibration to negate CSA input offset error?
  4. How much can the input VCM change? For single-stage CSAs, as VCM changes so can the effective VREF voltage since current can flow from VCM through input pins and to the REF pin. Thus, a fluctuating VCM of even a few volts can further reduce dynamic range.