SLYA042 July   2024 FDC1004 , FDC1004-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 CSAs and Input Bias Stage
  6. 3 CSA and Gain Error Factor
  7. 4 Applications for Resistance at Input Pins of Current Sense Amplifiers
    1. 4.1 Input Resistance Design Considerations
  8. 5 Applications for Input Resistance at Reference Pins of Current Sense Amplifiers
    1. 5.1 Bidirectional CSA and Applications
    2. 5.2 Driving CSA Reference Pin With High-Resistance Source Voltage
    3. 5.3 Input Resistance at Reference Pin Design Considerations
  9. 6 Design Procedure and Error Calculation for External Input Resistance on CSA
    1. 6.1 Calculating eEXT for INA185A4 With 110Ω Input Resistors
  10. 7 Design Procedure for Input Resistance on Capacitively-Coupled Current Sense Amplifier
    1. 7.1 Bench Verification of Input eEXT for Capacitively-Coupled Current Sense Amplifiers
  11. 8 Design Procedure for Input Resistance at CSA Reference Pins
  12. 9 Input Resistance Error Test with INA185 Over Temperature
    1. 9.1 Schematic
    2. 9.2 Methods
    3. 9.3 Theoretical Model
    4. 9.4 Data for INA185A4 with 110Ω Input Resistors
      1. 9.4.1 Data Calculations
    5. 9.5 Analysis
  13. 10Input Resistance Error Test with INA191 Over Temperature
    1. 10.1 Schematic
    2. 10.2 Methods
    3. 10.3 Theoretical Model
    4. 10.4 Data for INA191A4 With 2.2kΩ Input Resistors
      1. 10.4.1 Data Analysis
    5. 10.5 Analysis
  14. 11Derivation of VOS, EXT for a Single Stage Current Sense Amplifier (CSA)
  15. 12Summary
  16. 13References

10.5 Analysis

The INA191 performed very closely as expected according to the theoretical calculations. Prediction errors for EG, EXT (approximately 0.06%) and EG, EXT Drift (approximately 0.25ppm/°C) were precise and show little change over temperature. These errors were small enough that the errors can come simply from variation in REXT and/or ammeter accuracy.

EG, Drift performance for INA191 was outside of its specification of 7ppm/°C, although this does not affect analysis primarily because the critical value of measurement was eEXT, which is a delta measurement with and without REXT. Certainly, the most probably reason for this large gain error drift was an imperfect calibration of the shunt resistor.

VOS, EXT was reasonable at around 2.4µV at 125°C, but VOS, EXT Drift was significant at -45nV/°C when increasing temperature to 125°C. As expected, VOS, EXT Drift reduces and flips polarity to 16.9nV/°C when decreasing temperature. Further efforts to reduce this drift can by increasing CDIFF.

Considered that the theoretical model used typical RDIFF values over temperature, yet performance was just below model boundaries. This indicates that for future designs, sufficient margin can be established to understand worst-case gain error. Downshifting (or reducing) the RDIFF curve by 30% can provide ample margin.